Cypress Semiconductor CY8C24894 Especificaciones descargar pdf (Pagina 3)

CY8C24894

Document Number: 001-53754 Rev. *F Page 3 of 50

PSoC Functional Overview

The PSoC family consists of many Programmable

System-on-Chip with on-chip controller devices. All PSoC family

devices are designed to replace traditional microcontroller units

(MCUs), system ICs, and the numerous discrete components

that surround them. Configurable analog, digital, and inter-

connect circuitry enable a high level of integration in a host of

industrial, consumer, and communication applications.

This architecture allows the user to create customized peripheral

configurations that match the requirements of each individual

application. Additionally, a fast CPU, Flash program memory,

SRAM data memory, and configurable I/O are included in a

range of convenient pinouts and packages.

The PSoC architecture, as illustrated in the Logic Block Diagram

on page 1, is comprised of four main areas: PSoc Core, digital

system, analog system, and system resources. Configurable

global busing allows all the device resources to be combined into

a complete custom system. The PSoC CY8C24x94 devices can

have up to seven I/O ports that connect to the global digital and

analog interconnects, providing access to four digital blocks and

six analog blocks.

The PSoC Core

The PSoC Core is a powerful engine that supports a rich feature

set. The core includes a CPU, memory, clocks, and configurable

GPIOs.

The M8C CPU core is a powerful processor with speeds up to

24 MHz, providing a four-MIPS 8-bit Harvard architecture micro-

processor. The CPU uses an interrupt controller with up to 20

vectors, to simplify programming of real-time embedded events.

Program execution is timed and protected using the included

sleep timer and watchdog timer (WDT).

Memory encompasses 16 KB of flash for program storage, 1 KB

of SRAM for data storage, and up to 2 KB of emulated EEPROM

using the flash. Program flash has four protection levels on

blocks of 64 bytes, allowing customized software IP protection.

The PSoC device incorporates flexible internal clock generators,

including a 24-MHz internal main oscillator (IMO) accurate to

±4% over temperature and voltage. The 24-MHz IMO can also

be doubled to 48 MHz for use by the digital system. A low power

32-kHz internal low-speed oscillator (ILO) is provided for the

sleep timer and WDT. The clocks, together with programmable

clock dividers (as system resources), provide the flexibility to

integrate almost any timing requirement into the PSoC device.

PSoC GPIOs provide connection to the CPU, digital resources,

and analog resources of the device. Each pin’s drive mode may

be selected from eight options, allowing great flexibility in

external interfacing. Every pin is also capable of generating a

system interrupt.

The Digital System

The digital system is composed of four digital PSoC blocks. Each

block is an 8-bit resource used alone or combined with other

blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are

called user modules.

Figure 1. Digital System Block Diagram

Digital peripheral configurations include those listed below.

■ PWMs (8- to 32-bit)

■ PWMs with Dead band (8- to 24-bit)

■ Counters (8- to 32-bit)

■ Timers (8- to 32-bit)

■ Full- or half-duplex 8-bit UART with selectable parity

■ SPI master and slave

■ I

C master, slave, or multimaster (implemented in a dedicated

C block)

■ Cyclic redundancy checker/generator (16-bit)

■ Infrared Data Association (IrDA)

■ PRS generators (8- to 32-bit)

The digital blocks can be connected to any GPIO through a

series of global buses that can route any signal to any pin. The

buses also allow signal multiplexing and performing logic opera-

tions. This configurability frees your designs from the constraints

of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of

blocks varies by PSoC device family. This allows you the

optimum choice of system resources for your application. Family

resources are shown in Table 1 on page 5.

DIGITAL SYSTEM

To System Bus

Digital PSoC Block Array

To Analog

System

Row Input

Configuration

Row Output

Configuration

Row 0

DBB00 DBB01 DCB02 DCB03

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0]

Global Digital

Interconnect

Port 1

Port 0

Port 3

Port 2

Port 5

Port 4

Port 7

1 2 3 4 5 6 7 8 ... 49 50

Comentarios a estos manuales

Sin comentarios

Cypress Semiconductor CY8C24894 Especificaciones Pagina 3

Comentarios a estos manuales

Relacionado con productos y manuales para No Cypress Semiconductor CY8C24894