Cypress Semiconductor CY7C1365C Manual de usuario descargar pdf (Pagina 8)

CY7C1361V25

CY7C1363V25

CY7C1365V25

PRELIMINARY

Burst Sequences

The CY7C1361V25/CY7C1365V25/CY7C1363V25 provides

a two-bit wraparound counter, fed by A

[1:0]

, that implements

either an interleaved or linear burst sequence. to support pro-

cessors that follow a linear burst sequence. The burst se-

quence is user selectable through the MODE input.

Asserting ADV

LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both read and write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ HIGH

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed. Ac-

cesses pending when entering the “sleep” mode are not con-

sidered valid nor is the completion of the operation guaran-

teed. The device must be deselected prior to entering the

“sleep” mode. CE

, CE

, ADSP, and ADSC must remain

inactive for the duration of t

ZZREC

after the ZZ input returns

LOW. Leaving ZZ unconnected defaults the device into an ac-

tive state.

Interleaved Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

[1:0]

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

[1:0]

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 29 30

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