Cypress Semiconductor CY7C1365C Manual de usuario descargar pdf (Pagina 6)

CY7C1361V25

CY7C1363V25

CY7C1365V25

PRELIMINARY

Pin Definitions (119-Ball BGA)

Name I/O Description

Input-

Synchronous

Address Inputs used to select one of the address locations. Sampled at the

rising edge of the CLK if ADSP

or ADSC is active LOW, and CE

, and

are sampled active. A

[1:0]

feed the 2-bit counter.

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte

writes to the SRAM. Sampled on the rising edge of CLK.

GW Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge

of CLK, a global write is conducted (ALL bytes are written, regardless of the

values on BW

a,b,c,d

and BWE).

BWE Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This

signal must be asserted LOW to conduct a byte write.

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used

to increment the burst counter when ADV

is asserted LOW, during a burst

operation.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE

and CE

to select/deselect the device. ADSP is ignored

if CE

is HIGH.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used

in conjunction with CE

and CE

to select/deselect the device. This pin will be

used for address expansion to the next density SRAM.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE

and

to select/deselect the device.

OE Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Controls the direction of the

I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH,

I/O pins are three-stated, and act as input data pins. OE

is masked during the

first clock of a read cycle when emerging from a deselected state.

ADV Input-

Synchronous

Advance Input signal, sampled on the rising edge of CLK. When asserted, it

automatically increments the address in a burst cycle.

ADSP Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK. When

asserted LOW, A is captured in the address registers. A

[1:0]

are also loaded

into the burst counter. When ADSP

and ADSC are both asserted, only ADSP

is recognized. ASDP

is ignored when CE

is deasserted HIGH.

ADSC Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK. When

asserted LOW, A

[x:0]

is captured in the address registers. A

[1:0]

are also loaded

into the burst counter. When ADSP

and ADSC are both asserted, only ADSP

is recognized.

MODE Input-

Static

Selects burst order. When tied to GND selects linear burst sequence. When

tied to V

DDQ

or left floating selects interleaved burst sequence. This is a strap

pin and should remain static during device operation.

ZZ Input-

Asynchronous

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical

“sleep” condition with data integrity preserved.

NC,DQ

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register

that is triggered by the rising edge of CLK. As outputs, they deliver the data

contained in the memory location specified by A during the previous clock rise

of the read cycle. The direction of the pins is controlled by OE

. When OE is

asserted LOW, the pins behave as outputs. When HIGH, DQ

and DP

are

placed in a three-state condition.

On the CY7C1365 SRAM, these are not connect pins.

1 2 3 4 5 6 7 8 9 10 11 ... 29 30

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