Cypress Semiconductor CY7C1365C Manual de usuario Pagina 21

  • Descarga
  • Añadir a mis manuales
  • Imprimir
  • Pagina
    / 30
  • Tabla de contenidos
  • MARCADORES
  • Valorado. / 5. Basado en revisión del cliente
Vista de pagina 20
CY7C1361V25
CY7C1363V25
CY7C1365V25
PRELIMINARY
21
Switching Characteristics
Over the Operating Range
[12, 13, 14]
-133 -117 -100 -80
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
CYC
Clock Cycle Time 7.5 8.5 10.0 12.5 ns
t
CH
Clock HIGH 1.9 3.0 3.2 4.0 ns
t
CL
Clock LOW 1.9 3.0 3.2 4.0 ns
t
AS
Address Set-Up Before CLK Rise 1.5 2 2 2.0 ns
t
AH
Address Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
t
CO
Data Output Valid After CLK Rise 6.5 7.5 8.5 10.0 ns
t
DOH
Data Output Hold After CLK Rise 1.5 1.5 1.5 1.5 ns
t
ADS
ADSP, ADSC Set-Up Before CLK
Rise
1.5 2 2 2.0 ns
t
ADH
ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
t
WES
BWE, GW, BW[3:0] Set-Up Before
CLK Rise
1.5 2 2 2.0 ns
t
WEH
BWE, GW, BW[3:0] Hold After CLK
Rise
0.5 0.5 0.5 0.5 ns
t
ADVS
ADV Set-Up Before CLK Rise 1.5 2.0 2.0 2.0 ns
t
ADVH
ADV Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
t
DS
Data Input Set-Up Before CLK Rise 1.5 2.0 2.0 2.0 ns
t
DH
Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
t
CES
Chip enable Set-Up 1.5 2 2 2.0 ns
t
CEH
Chip enable Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
t
CHZ
Clock to High-Z
[13, 14, 15]
0 3.5 0 3.5 0 3.5 0 3.5 ns
t
CLZ
Clock to Low-Z
[13, 14, 15]
0 0 0 0 ns
t
EOHZ
OE HIGH to Output High-Z
[13, 14]
3.5 3.5 3.5 3.5 ns
t
EOLZ
OE LOW to Output Low-Z
[13, 14]
0 0 0 0 ns
t
EOV
OE LOW to Output Valid
[13, 14]
3.5 4.2 5.0 5.0 ns
Notes:
12. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified I
OL
/I
OH
and load capacitance. Shown in (a), (b) and (c) of AC test loads.
13. t
CHZ
, t
CLZ
, t
OEV
, t
EOLZ
, and t
EOHZ
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
200 mV from steady-
state voltage.
14. At any given voltage and temperature, t
CHZ
(max.) is less than t
CLZ
(min.).
15. This parameter is sampled and not 100% tested.
Vista de pagina 20
1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 29 30

Comentarios a estos manuales

Sin comentarios