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Cypress Semiconductor FLEx36 CY7C0850AV Manual de usuario Pagina 12

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CY7C0850AV,CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document #: 38-06070 Rev. *K Page 12 of 36
Notes
15. 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits
16. The “X” in this diagram represents the counter upper bits
Figure 5. Programmable Counter-Mask Register Operation
[15, 16]
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
H
H
L
H
11
0s
1
0
1
0
101
00
Xs
1
X
0
X
0X0
11
Xs
1
X
1
X
1X1
00
Xs
1
X
0
X
0X0
Masked Address Unmasked Address
Mask
Register
bit-0
Address
Counter
bit-0
CNTINT
Example:
Load
Counter-Mask
Register = 3F
Load
Address
Counter = 8
Max
Address
Register
Max + 1
Address
Register
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