Cypress Semiconductor FLEx36 CY7C0850AV Manual de usuario descargar pdf (Pagina 1)

CY7C0850AV,CY7C0851V/CY7C0851AV

CY7C0852V/CY7C0852AV

CY7C0853V/CY7C0853AV

FLEx36™ 3.3 V 32K/64K/128K/256K x 36

Synchronous Dual-Port RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-06070 Rev. *K Revised October 12, 2011

Features

■ True dual-ported memory cells that allow simultaneous access

of the same memory location

■ Synchronous pipelined operation

■ Organization of 1-Mbit, 2-Mbit, 4-Mbit, and 9-Mbit devices

■ Pipelined output mode allows fast operation

■ 0.18-micron Complimentary metal oxide semiconductor

(CMOS) for optimum speed and power

■ High-speed clock to data access

■ 3.3 V low power

❐ Active as low as 225 mA (typ)

❐ Standby as low as 55 mA (typ)

■ Mailbox function for message passing

■ Global master reset

■ Separate byte enables on both ports

■ Commercial and industrial temperature ranges

■ IEEE 1149.1-compatible Joint test action group (JTAG)

boundary scan

■ 172-Ball fine-pitch ball grid array (FBGA) (1 mm pitch)

(15 mm × 15 mm)

■ 176-Pin thin quad plastic flatpack (TQFP) (24 mm × 24 mm ×

1.4 mm)

■ Counter wrap around control

❐ Internal mask register controls counter wrap-around

❐ Counter-interrupt flags to indicate wrap-around

❐ Memory block retransmit operation

■ Counter readback on address lines

■ Mask register readback on address lines

■ Dual chip enables on both ports for easy depth expansion

Functional Description

The FLEx36™ family includes 1M, 2M, 4M, and 9M pipelined,

synchronous, true dual-port static RAMs that are high-speed,

low-power 3.3 V CMOS. Two ports are provided, permitting

independent, simultaneous access to any location in memory.

The result of writing to the same location by more than one port

at the same time is undefined. Registers on control, address, and

data lines allow for minimal setup and hold time.

During a Read operation, data is registered for decreased cycle

time. Each port contains a burst counter on the input address

address, the counter increments the address internally (more

details to follow). The internal Write pulse width is independent

of the duration of the R/W

input signal. The internal Write pulse

is self-timed to allow the shortest possible cycle times.

A HIGH on CE0

or LOW on CE1 for one clock cycle powers down

the internal circuitry to reduce the static power consumption. One

cycle with chip enables asserted is required to reactivate the

outputs.

Additional features include: readback of burst-counter internal

address value on address lines, counter-mask registers to

control the counter wrap-around, counter interrupt (CNTINT

)

flags, readback of mask register value on address lines,

retransmit functionality, interrupt flags for message passing,

JTAG for boundary scan, and asynchronous Master Reset

(MRST).

The CY7C0853V/CY7C0853AV device in this family has limited

features. Please see See “Address Counter and Mask Register

Operations” on page 9. for details.

Table 1. Product Selection Guide

Density

1-Mbit

(32K x 36)

2-Mbit

(64K x 36)

4-Mbit

(128K x 36)

9-Mbit

(256K x 36)

Part number CY7C0850AV CY7C0851V/

CY7C0851AV

CY7C0852V/

CY7C0852AV

CY7C0853V/

CY7C0853AV

Max. speed (MHz) 167 167 167 133

Max. access time - clock to data (ns) 4.0 4.0 4.0 4.7

Typical operating current (mA) 225 225 225 270

Package 176TQFP

172FBGA

176TQFP

172FBGA

176TQFP

172FBGA

1 2 3 4 5 6 ... 35 36

Indice de contenidos

Pagina 1 - Synchronous Dual-Port RAM

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVFLEx36™ 3.3 V 32K/64K/128K/256K x 36Synchronous Dual-Port RAMCypress Semicondu

Pagina 2

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 10 of 36Counter InterruptThe counter interr

Pagina 3

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 11 of 36Note14. 9M device has 18 address bi

Pagina 4

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 12 of 36Notes15. 9M device has 18 address b

Pagina 5

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 13 of 36IEEE 1149.1 Serial Boundary Scan (J

Pagina 6

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 14 of 36Maximum Ratings Exceeding maximum r

Pagina 7

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 15 of 36Figure 6. AC Test Load and Wavefor

Pagina 8

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 16 of 36tOEOutput enable to data valid – 4.

Pagina 9 - Counter Load Operation

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 17 of 36 JTAG Timing Parameter Description1

Pagina 10 - CY7C0853V/CY7C0853AV

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 18 of 36Switching Waveforms Figure 8. Mas

Pagina 11

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 19 of 36Figure 10. Bank Select Read[31, 32

Pagina 12

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 2 of 36Logic Block Diagram [1]A0L–A17LCLKLA

Pagina 13 - Performing a TAP Reset

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 20 of 36Figure 12. Read-to-Write-to-Read

Pagina 14

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 21 of 36Figure 14. Write with Address Coun

Pagina 15

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 22 of 36Figure 16. Disabled to Write- to-

Pagina 16

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 23 of 36Figure 18. Read-to-Readback to Rea

Pagina 17

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 24 of 36Figure 19. Counter Reset[42, 43, 4

Pagina 18

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 25 of 36Figure 20. Readback State of Addre

Pagina 19

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 26 of 36Figure 21. Left_Port (L_Port) Writ

Pagina 20

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 27 of 36Figure 22. Counter Interrupt and R

Pagina 21

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 28 of 36Figure 23. MailBox Interrupt Timin

Pagina 22

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 29 of 36Ordering InformationCypress offers

Pagina 23

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 3 of 36ContentsPin Configurations ...

Pagina 24

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 30 of 36Ordering Code DefinitionCY7CXXXXCom

Pagina 25

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 31 of 36Package DiagramsFigure 24. 172-Bal

Pagina 26

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 32 of 36Figure 25. 176-Pin Thin Quad Flat

Pagina 27

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 33 of 36Acronyms Document ConventionsUnits

Pagina 28

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 34 of 36Document History PageDocument Title

Pagina 29

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 35 of 36*J 3093275 11/23/2010 ADMU Added ne

Pagina 30

Document #: 38-06070 Rev. *K Revised October 12, 2011 Page 36 of 36All products and company names mentioned in this document may be the trademarks of

Pagina 31

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 4 of 36Pin Configurations Figure 1. 172-Ba

Pagina 32

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 5 of 36Figure 2. 172-Ball BGA (Top View)Pi

Pagina 33 - Units of Measure

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 6 of 36Figure 3. 176-Pin Thin Quad Flat Pa

Pagina 34

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 7 of 36Pin DefinitionsLeft Port Right Port

Pagina 35

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 8 of 36Master ResetThe FLEx36 family device

Pagina 36 - PSoC Solutions

CY7C0850AV,CY7C0851V/CY7C0851AVCY7C0852V/CY7C0852AVCY7C0853V/CY7C0853AVDocument #: 38-06070 Rev. *K Page 9 of 36Address Counter and Mask Register Op

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