Cypress Semiconductor CYDC128B16 Manual de usuario descargar pdf (Pagina 19)

CYDC128B16

Document #: 001-01638 Rev. *H Page 19 of 29

Switching Waveforms

Figure 3. Read Cycle No.1 (Either Port Address Access)

[6, 7, 8]

Figure 4. Read Cycle No.2 (Either Port CE/OE Access)

[6, 9, 10]

Figure 5. Read Cycle No. 3 (Either Port)

[6, 8, 11, 12]

Notes

6. R/W

is HIGH for read cycles.

7. Device is continuously selected CE

= V

and UB or LB = V

. This waveform cannot be used for semaphore reads.

8. OE

= V

9. Address valid prior to or coincident with CE

transition LOW.

10. To access RAM, CE

= V

, UB or LB = V

, SEM = V

. To access semaphore, CE = V

, SEM = V

11. R/W

must be HIGH during all address transitions.

12. A write occurs during the overlap (t

SCE

or t

PWE

) of a LOW CE or SEM and a LOW UB or LB.

OHA

DATA VALIDPREVIOUS DATA VALID

DATA OUT

ADDRESS

OHA

ACE

LZOE

DOE

HZOE

HZCE

DATA VALID

LZCE

DATA OUT

CE and

or UB

CURRENT

UB or LB

DATA OUT

ADDRESS

OHA

LZCE

ABE

HZCE

ACE

LZCE

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