Cypress Semiconductor CY7C68301C Manual de usuario descargar pdf (Pagina 9)

CY7C68300C, CY7C68301C

CY7C68320C, CY7C68321C

Document Number: 001-05809 Rev. *K Page 9 of 44

Pin Descriptions

The following table lists the pinouts for the 56-pin SSOP, 56-pin QFN, and 100-pin TQFP package options for the AT2LP. Refer to the

Pin Diagrams on page 5 for differences between the 68300C/01C and 68320C/321C pinouts for the 56-pin packages.

Table 1. AT2LP Pin Descriptions

Note Italic pin names denote pin functionality during CY7C68300A compatibility mode

100

TQFP

QFN

SSOP

Pin Name

Type

Default State

at Startup

Pin Description

1 55 6 V

PWR V

. Connect to 3.3 V power source.

2 56 7 GND GND Ground.

3 1 8 IORDY I

[1]

Input ATA control. Apply a 1 k pull up to 3.3 V.

4 2 9 DMARQ I

[1]

Input ATA control.

N/A N/A GND Ground.

9 3 10 AV

PWR Analog V

. Connect to V

through the shortest path

possible.

10 4 11 XTALOUT Xtal Xtal 24 MHz crystal output. (See XTALIN, XTALOUT on page 13).

11 5 12 XTALIN Xtal Xtal 24 MHz crystal input. (See XTALIN, XTALOUT on page 13).

12 6 13 AGND GND Analog ground. Connect to ground with as short a path as

possible.

N/A N/A NC No connect.

16 7 14 V

PWR V

. Connect to 3.3 V power source.

17 8 15 DPLUS I/O High Z USB D+ signal (See DPLUS, DMINUS on page 13).

18 9 16 DMINUS I/O High Z USB D– signal (See DPLUS, DMINUS on page 13).

19 10 17 GND GND Ground.

20 11 18 V

PWR V

. Connect to 3.3 V power source.

21 12 19 GND GND Ground.

22 N/A N/A SYSIRQ I Input USB interrupt request. (See SYSIRQ on page 13). Active

HIGH. Connect to GND if functionality is not used.

N/A N/A GND GND Ground.

[2]

20 PWR500#

[3]

(PU 10K)

O bMaxPower request granted indicator.

(See PWR500# on page 15). Active LOW.

N/A for CY7C68320C/CY7C68321C 56-pin packages.

27 14 21 GND (RESERVED) Reserved. Tie to GND.

28 N/A N/A NC No connect.

29 15 22 SCL O Active for

several ms at

startup.

Clock signal for I

C interface. (See SCL, SDA on page 13).

Apply a 2.2k pull up resistor.

Notes

1. If byte 8, bit 4 of the EEPROM is set to ‘0’, the ATA interface pins are only active when VBUS_ATA_EN is asserted. See VBUS_ATA_ENABLE on page 15.

2. The General Purpose inputs can be enabled on ATAPUEN, PWR500#, and DRVPWRVLD via EEPROM byte 8, bit 7 on CY7C68320C/CY7C68321C.

3. A ‘#’ sign after the pin name indicates that it is active LOW.

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