Cypress Semiconductor CY7C68301C Manual de usuario descargar pdf (Pagina 17)

CY7C68300C, CY7C68301C

CY7C68320C, CY7C68321C

Document Number: 001-05809 Rev. *K Page 17 of 44

2 bmATACBActionSelect This field controls the execution of the ATACB according to the bitfield values:

Bit 7 IdentifyPacketDevice – This bit indicates that the data phase of the

command contains ATAPI (0xA1) or ATA (0xEC) IDENTIFY device data. Setting

IdentifyPacketDevice when the data phase does not contain IDENTIFY device

data results in unspecified device behavior.

0 = Data phase does not contain IDENTIFY device data

1 = Data phase contains ATAPI or ATA IDENTIFY device data

Bit 6 UDMACommand – This bit enables supported UDMA device transfers.

Setting this bit when a non-UDMA capable device is attached results in undeter-

mined behavior.

0 = Do not use UDMA device transfers (only use PIO mode)

1 = Use UDMA device transfers

Bit 5 DEVOverride – This bit determines whether the DEV bit value is taken from

the value assigned to the LUN during startup or from the ATACB.

0 = The DEV bit is taken from the value assigned to the LUN during startup

1 = The DEV bit is taken from the ATACB field 0x0B, bit 4

Bit 4 DErrorOverride – This bit controls the device error override feature. This bit

must not be set during a bmATACBActionSelect TaskFileRead.

0 = Data accesses are halted if a device error is detected

1 = Data accesses are not halted if a device error is detected

Bit 3 PErrorOverride – This bit controls the phase error override feature. This bit

must not be set during a bmATACBActionSelect TaskFileRead.

0 = Data accesses are halted if a phase error is detected

1 = Data accesses are not halted if a phase error is detected

Bit 2 PollAltStatOverride – This bit determines whether or not the Alternate Status

0 = The AltStat register is polled until BSY=0 before proceeding with the ATACB

operation

1 = The ATACB operation is executed without polling the AltStat register.

Bit 1 DeviceSelectionOverride – This bit determines when the device selection is

performed in relation to the command register write accesses.

0 = Device selection is performed before command register write accesses

1 = Device selection is performed following command register write accesses

Bit 0 TaskFileRead – This bit determines whether or not the TaskFile register data

selected in bmATACBRegisterSelect is returned. If this bit is set, the dCBWData-

TransferLength field must be set to 8.

0 = Execute ATACB command and data transfer (if any)

1 = Only read TaskFile registers selected in bmATACBRegisterSelect and return

0x00h for all others. The format of the 8 bytes of returned data is as follows:

❐ Address offset 0x00 (0x3F6) – Alternate Status

❐ Address offset 0x01 (0x1F1) – Features/Error

❐ Address offset 0x02 (0x1F2) – Sector Count

❐ Address offset 0x03 (0x1F3) – Sector Number

❐ Address offset 0x04 (0x1F4) – Cylinder Low

❐ Address offset 0x05 (0x1F5) – Cylinder High

❐ Address offset 0x06 (0x1F6) – Device/Head

❐ Address offset 0x07 (0x1F7) – Command/Status

Table 6. ATACB Field Descriptions (continued)

Byte Field Name Field Description

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 43 44

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