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Cypress Semiconductor CY7C68301C Manual de usuario Pagina 11

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CY7C68300C, CY7C68301C
CY7C68320C, CY7C68321C
Document Number: 001-05809 Rev. *K Page 11 of 44
67 33 40 INTRQ I
[6]
Input ATA interrupt request.
68 34 41 DA0 O/Z
[6]
Driven HIGH
after 2 ms
delay
ATA address.
69 35 42 DA1 O/Z
[6]
Driven HIGH
after 2 ms
delay
ATA address.
70
[7]
36
[7]
43 DRVPWRVLD
(DA2)
I Input Device presence detect. (See DRVPWRVLD on page 14).
Configurable logical polarity is controlled by EEPROM address
0x08. This pin must be pulled HIGH if functionality is not used.
Alternate function. Input when the EEPROM configuration
byte 8 has bit 7 set to ‘1’. The input value is reported through
EP1IN (byte 0, bit 0).
71 37 44 CS0# O/Z
[6]
Driven HIGH
after 2 ms
delay
ATA chip select.
72 38 45 CS1# O/Z
[6]
Driven HIGH
after 2 ms
delay
ATA chip select.
73 39 46 DA2
(VBUS_PWR_VALID)
O/Z
[6]
Driven HIGH
after 2 ms
delay
ATA address.
74 40 47 ARESET# O/Z
[6]
ATA reset.
75 41 48 GND GND Ground.
76 N/A N/A NC NC No connect.
77 42 49 RESET# I Input Chip reset (See RESET# on page 15).
78 43 50 V
CC
PWR V
CC
. Connect to 3.3 V power source.
79 44 51 VBUS_ATA_ENABLE
(ATA_EN)
I Input VBUS detection (See VBUS_ATA_ENABLE on page 15).
80 45 52 DD8 I/O
[6]
High Z ATA data bit 8.
81 46 53 DD9 I/O
[6]
High Z ATA data bit 9.
82 47 54 DD10 I/O
[6]
High Z ATA data bit 10.
83 48 55 DD11 I/O
[6]
High Z ATA data bit 11.
84 N/A N/A GND Ground.
85 N/A N/A V
CC
PWR V
CC
. Connect to 3.3 V power source.
86
87
N/A N/A NC NC No connect.
88
89
90
91
92
93
36
[7]
13
[7]
54
[7]
N/A GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
I/O
[7]
General Purpose I/O pins (See GPIO Pins on page 14). The
GPIO pins must be tied to GND if functionality is not used.
94 N/A N/A GND GND Ground.
Table 1. AT2LP Pin Descriptions (continued)
Note Italic pin names denote pin functionality during CY7C68300A compatibility mode
100
TQFP
56
QFN
56
SSOP
Pin Name
Pin
Type
Default State
at Startup
Pin Description
Notes
6. If byte 8, bit 4 of the EEPROM is set to ‘0’, the ATA interface pins are only active when VBUS_ATA_EN is asserted. See VBUS_ATA_ENABLE on page 15.
7. The General Purpose inputs can be enabled on ATAPUEN, PWR500#, and DRVPWRVLD via EEPROM byte 8, bit 7 on CY7C68320C/CY7C68321C.
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