Cypress Semiconductor CY7C1365C Manual de usuario descargar pdf (Pagina 23)

CY7C1365C

Document Number: 001-74584 Rev. *C Page 23 of 30

Figure 4. Write Cycle Timing

[22, 23]

Timing Diagrams (continued)

CYC

CLK

ADH

ADS

ADDRESS

CEH

CES

High-Z

BURST READ BURST WRITE

D(A2) D(A2 + 1) D(A2 + 1)

D(A1)

D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

A2 A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

ADH

ADS

ADH

ADS

OEHZ

ADVH

ADVS

WEH

WES

WEH

WES

Byte write signals are ignored for first cycle when

ADSP initiates burst.

ADSC extends burst.

ADV suspends burst.

DON’T CARE UNDEFINED

ADSP

ADSC

BWE,

[A:D]

ADV

Data in (D)

Data Out (Q)

Notes

22. Full width write can be initiated by either GW

LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

23. The data bus (Q) remains in High Z following a Write cycle unless an ADSP

, ADSC, or ADV cycle is performed.

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 29 30

9-Mbit (256 K × 32) 1
Flow-Through Sync SRAM 1
CY7C1365C 10
Disabling the JTAG Feature 11
Test Access Port (TAP) 11
Performing a TAP Reset 11
TAP Registers 11
TAP Instruction Set 12
Ordering Code Definitions 26
Units of Measure 28
Products 30
PSoC Solutions 30

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