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Cypress Semiconductor CY7C1365C Manual de usuario Pagina 15

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CY7C1365C
Document Number: 001-74584 Rev. *C Page 15 of 30
3.3 V TAP AC Test Conditions
Input pulse levels ...............................................V
SS
to 3.3 V
Input rise and fall times ...................................................1 ns
Input timing reference levels ......................................... 1.5 V
Output reference levels ................................................ 1.5 V
Test load termination supply voltage ............................ 1.5 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................V
SS
to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .......................... 1.25 V
2.5 V TAP AC Output Load Equivalent
TAP AC Switching Characteristics
Over the Operating Range
Parameter
[8, 9]
Parameter Min Max Unit
Clock
t
TCYC
TCK clock cycle time 50 – ns
t
TF
TCK clock frequency – 20 MHz
t
TH
TCK clock HIGH time 20 – ns
t
TL
TCK clock LOW time 20 – ns
Output Times
t
TDOV
TCK clock LOW to TDO valid – 10 ns
t
TDOX
TCK clock LOW to TDO invalid 0 – ns
Set-up Times
t
TMSS
TMS setup to TCK clock rise 5 – ns
t
TDIS
TDI setup to TCK clock rise 5 – ns
t
CS
Capture setup to TCK rise 5 – ns
Hold Times
t
TMSH
TMS hold after TCK clock rise 5 – ns
t
TDIH
TDI hold after clock rise 5 – ns
t
CH
Capture hold after clock rise 5 – ns
TDO
1.5V
20pF
Z = 50Ω
O
50Ω
TDO
1.25V
20pF
Z = 50Ω
O
50Ω
Notes
8. t
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
9. Test conditions are specified using the load in TAP AC test conditions. t
R
/t
F
= 1 ns.
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