Document Number: 001-74584 Rev. *C Page 21 of 30
Switching Characteristics
Over the Operating Range
Parameter
[15, 16]
Description
-133
Unit
Min Max
t
POWER
V
DD
(typical) to the first access
[17]
1–ms
Clock
t
CYC
Clock cycle time 7.5 – ns
t
CH
Clock HIGH 3.0 – ns
t
CL
Clock LOW 3.0 – ns
Output Times
t
CDV
Data output valid after CLK rise – 6.5 ns
t
DOH
Data output hold after CLK rise 2.0 – ns
t
CLZ
Clock to low Z
[18, 19, 20]
0–ns
t
CHZ
Clock to high Z
[18, 19, 20]
–3.5ns
t
OEV
OE LOW to output valid – 3.5 ns
t
OELZ
OE LOW to output low Z
[18, 19, 20]
0–ns
t
OEHZ
OE HIGH to output high Z
[18, 19, 20]
–3.5ns
Set-up Times
t
AS
Address set-up before CLK rise 1.5 – ns
t
ADS
ADSP, ADSC set-up before CLK rise 1.5 – ns
t
ADVS
ADV set-up before CLK rise 1.5 – ns
t
WES
GW, BWE, BW
[A:D]
set-up before CLK rise 1.5 – ns
t
DS
Data input set-up before CLK rise 1.5 – ns
t
CES
Chip enable set-up 1.5 – ns
Hold Times
t
AH
Address hold after CLK rise 0.5 – ns
t
ADH
ADSP, ADSC hold after CLK rise 0.5 – ns
t
WEH
GW
,
BWE
,
BW
[A:D]
hold after CLK rise
0.5 – ns
t
ADVH
ADV hold after CLK rise 0.5 – ns
t
DH
Data input hold after CLK rise 0.5 – ns
t
CEH
Chip enable hold after CLK rise 0.5 – ns
Notes
15. Timing reference level is 1.5 V when V
DDQ
= 3.3 V and is 1.25 V when V
DDQ
= 2.5 V.
16. Test conditions shown in (a) of Figure 2 on page 20 unless otherwise noted.
17. This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD(minimum)
initially before a Read or Write operation can
be initiated.
18. t
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of Figure 2 on page 20. Transition is measured ±200 mV from steady-state voltage.
19. At any given voltage and temperature, t
OEHZ
is less than t
OELZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
20. This parameter is sampled and not 100% tested.
(36 paginas)
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