CY7C601xx
CY7C602xx
Document 38-16016 Rev. *C Page 51 of 62
Interrupt Mask Registers
The Interrupt Mask Registers (INT_MSKx) are used to enable
the individual interrupt sources’ ability to create pending inter-
rupts.
There are four Interrupt Mask Registers (INT_MSK0,
INT_MSK1, INT_MSK2, and INT_MSK3) which may be
referred to in general as INT_MSKx. If cleared, each bit in an
INT_MSKx register prevents a posted interrupt from becoming
a pending interrupt (input to the priority encoder). However, an
interrupt can still post even if its mask bit is zero. All INT_MSKx
bits are independent of all other INT_MSKx bits.
If an INT_MSKx bit is set, the interrupt source associated with
that mask bit may generate an interrupt that will become a
pending interrupt.
The Enable Software Interrupt (ENSWINT) bit in INT_MSK3[7]
determines the way an individual bit value written to an
INT_CLRx register is interpreted. When is cleared, writing 1's
to an INT_CLRx register has no effect. However, writing 0's to
an INT_CLRx register, when ENSWINT is cleared, will cause
the corresponding interrupt to clear. If the ENSWINT bit is set,
any 0's written to the INT_CLRx registers are ignored.
However, 1's written to an INT_CLRx register, while ENSWINT
is set, will cause an interrupt to post for the corresponding
interrupt.
Software interrupts can aid in debugging interrupt service
routines by eliminating the need to create system level inter-
actions that are sometimes necessary to create a hardware-
only interrupt.
Table 82. Interrupt Clear 1 (INT_CLR1) [0xDB] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field TCAP0 Prog Interval
Timer
1-ms Program-
mable Interrupt
Reserved
Read/Write R/W R/W R/W – ––– –
Default 0 0 0 0 000 0
When reading this register,
0 = There’s no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits will clear the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT
(Bit 7 of the INT_MSK3 Register) will post the corresponding hardware interrupt.
Table 83.Interrupt Clear 2 (INT_CLR2) [0xDC] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Reserved GPIO Port 4 GPIO Port 3 GPIO Port 2 Reserved INT2 16-bit Counter
Wrap
TCAP1
Read/Write – R/W R/W R/W –R/WR/W R/W
Default 0 0 0 0 000 0
When reading this register,
0 = There’s no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits will clear the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT
(Bit 7 of the INT_MSK3 Register) will post the corresponding hardware interrupt.
Table 84.Interrupt Mask 3 (INT_MSK3) [0xDE] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field ENSWINT Reserved
Read/Write R – – – – – – –
Default 0 0 0 0 000 0
Bit 7: Enable Software Interrupt (ENSWINT)
0= Disable. Writing 0's to an INT_CLRx register, when ENSWINT is cleared, will cause the corresponding interrupt to clear.
1= Enable. Writing 1's to an INT_CLRx register, when ENSWINT is set, will cause the corresponding interrupt to post.
Bit [6:0]: Reserved
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