Cypress Semiconductor enCoRe CY7C601xx Guía de usuario descargar pdf (Pagina 33)

CY7C601xx

CY7C602xx

Document 38-16016 Rev. *C Page 33 of 62

P1 Data

P2 Data

P3 Data

P4 Data

Table 45.P1 Data Register (P1DATA) [0x01] [R/W]

Bit # 7 6 5 4 3 2 1 0

Field P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2 P1.1 P1.0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0

This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading

from this register returns the current state of the Port 1 pins.

Bit 7: P1.7 Data

Bit [6:3]: P1.6–P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL)

Beside their use as the P1.6–P1.3 GPIOs, these pins can also be used for the alternate function as the SPI interface pins. To

configure the P1.6–P1.3 pins, refer to the P1.3–P1.6 Configuration Register (Table 57.)

Bit [2:0]: P1.2–P1.0

Table 46.P2 Data Register (P2DATA) [0x02] [R/W]

Bit # 7 6 5 4 3 2 1 0

Field P2.7–P2.2 P2.1–P2.0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 000

This register contains the data for Port 2. Writing to this register sets the bit values to be output on output enabled pins. Reading

from this register returns the current state of the Port 2 pins.

Bit [7:2]: P2 Data [7:2]

Bit [1:0]: P2 Data [1:0]

Table 47.P3 Data Register (P3DATA) [0x03] [R/W]

Bit # 7 6 5 4 3 2 1 0

Field P3.7–P3.2 P3.1–P3.0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 000

This register contains the data for Port 3. Writing to this register sets the bit values to be output on output enabled pins. Reading

from this register returns the current state of the Port 3 pins.

Bit [7:2]: P3 Data [7:2]

Bit [1:0]: P3 Data [1:0]

Table 48.P4 Data Register (P4DATA) [0x04] [R/W]

Bit # 7 6 5 4 3 2 1 0

Field Reserved P4.3–P4.0

Read/Write ––––R/W R/W R/W R/W

Default 00000 0 0 0

This register contains the data for Port 4. Writing to this register sets the bit values to be output on output-enabled pins. Reading

from this register returns the current state of the Port 2 pins.

Bit [7:4]: Reserved

Bit [3:0]: P4 Data [3:0]

P4.3–P4.0 only exist in the CY7C601xx

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 61 62

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Cypress Semiconductor enCoRe CY7C601xx Guía de usuario Pagina 33

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