Cypress Semiconductor Quad HOTLink II CYV15G0404RB Guía de usuario descargar pdf (Pagina 8)

Quad Independent Channel

HOTLink II™ CYV15G0404DXB

Video PHY Demonstration Board

Page 8 of 92

4.2 Clocking Architecture

The board has multiple clocking options to allow for flexible testing and configuration. On each channel, the user can select either

the on-board programmable clock, on-board 74.25-MHz crystal oscillator (for HD-SDI/SMPTE 292M), a clock provided by the

FPGA, or an external clock. The on-board programmable clock plays a useful role in the auto rate detection mechanism, which

dynamically reprograms the reference clock to the correct frequency, based on the incoming SDI data rate.

When transmitting the video test patterns generated by the FPGA, either the programmable clock, external clock or on-board

crystal oscillator (only for HD-SDI) should be used.

Table 4-1. Interface of Cable Drivers and Equalizers to HOTLink II Serial I/Os

HOTLink II Channel

Serial I/O of

HOTLink II Device

Interfacing Cable

Driver

Interfacing Equalizer Supported Standard

Channel A OUTA1+

Gennum GS1528 x HD-SDI and SD-SDI

INA1+ x Gennum GS1524

OUTA2+

No Cable Driver (SMA) x Supports any data rate from

195 Mb/s–1500 Mb/s

(not SMPTE-compliant)

INA2+

x No Equalizer (SMA)

Channel B OUTB1+ Gennum GS1528 x HD-SDI and SD-SDI

INB1+

x Gennum GS1524

OUTB2+ National CLC001 x SD-SDI

INB2+

x National CLC014

Channel C OUTC1+

Gennum GS1528 x HD-SDI and SD-SDI

INC1+

x Gennum GS1524

OUTC2+

Gennum GS9028 x SD-SDI

INC2+

x Gennum GS9024

Channel D OUTD1+ Gennum GS1528 x HD-SDI and SD-SDI

IND1+

x Gennum GS1524

OUTD2+

National CLC007 x SD-SDI

IND2+ x National CLC014

[+] Feedback

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 91 92

Comentarios a estos manuales

Sin comentarios

Cypress Semiconductor Quad HOTLink II CYV15G0404RB Guía de usuario Pagina 8

Comentarios a estos manuales

Relacionado con productos y manuales para Relojes De Pared Cypress Semiconductor Quad HOTLink II CYV15G0404RB