Cypress Semiconductor Quad HOTLink II CYV15G0404RB Guía de usuario Pagina 34
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Valorado. / 5. Basado en revisión del cliente
Quad Independent Channel
HOTLink II™ CYV15G0404DXB
Video PHY Demonstration Board
Page 34 of 92
Figure A-4. FPGA for Channel A and B
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
LS7652
Cypress Molson - FPGA1
2
04 12
G. Cosens
Size Dr aw in g Nu mb e r R evisio n
Date:
Fil e:
Sheet of
Drawn By:FPGA1.Sch Doc
7/ 6/ 2004
B
Linear Systems Ltd.
F1nC S
F1DATA0
F1nC ONFIG
F1DCLK
F1ASDI
TXDA[7 ..0]
TXDB[ 7..0]
TXCTA[1..0 ]
TXCTB[1..0]
TXCLKOA
TXCLKOB
TXCLKA
TXCLKB
RXDA[7..0]
RXDB[7..0]
RXSTA[2..0]
RXSTB[2..0]
RXCLKA+
RXCLK B+
RXCLKA-
RXCLK B-
SD/HD A
SD/HD B
CD/MUTEA
CD/MUTEB
PTXDA [9..0]
PTXDB[9..0]
PRXDA[9 ..0]
PRXDB[9..0]
F1DATA0
F1ASDI
F1DC LK
F1nCS
CL KOUT
IF C L K
LFIA
LFIB
SDI
SDO
SCL
SCSE
+3.3V +1.5V
DATA
2
DCL K
6
nCS
1
ASDI
5
VCC
8
VCC
7
VCC
3
GND
4
U4
EPCS4SI 8N
+3.3V
1 2
3 4
5 6
7 8
9 10
JP6
HEADER 5X2
+3.3V
F1nC E
F1nC S
F1DCLK
F1CONFI G_ D ON E
F1nC ONFIG
F1DATA0
F1ASDI
F1nC E
F1nC ONFIG
F1CONFI G_ D ON E
F1CONFIG_DONE
F1nC ON FIG
F1DATA0
F1DCLK
F1nC S
F1ASDI
F1DATA0
F1DCLK
F1n CS
F1ASDI
F1nC E F1CONFIG_DONE
F1nCONFIG
F1nSTATU S
R5
10K
R4
10K
R3
10K
+3.3 V
F1nCE
R6
10K
F1nC E
TXCLKA
TXCLKOA
TXDA 0
TXDA1
TXDA 2
TXDA 3
TXDA 4
TXDA 5
TXDA 6
TXDA 7
TXCTA0
TXCTA1
TXDA [7 . .0]
TXCTA[1..0 ]
RXCLKA+
RXCLKA-
RXDA0
RXDA1
RXDA2
RXDA3
RXDA4
RXDA5
RXDA6
RXDA7
RXSTA 0
RXSTA 1
RXDA[7..0]
RXSTA[2 .. 0]
PTXDA0
PTXDA1
PTXDA2
PTXDA3
PTXDA4
PTXDA5
PTXDA6
PTXDA7
PTXDA8
PTXDA9
PRXDA0
PRXDA1
PRXDA2
PRXDA3
PRXDA4
PRXDA5
PRXDA6
PRXDA7
PRXDA8
PRXDA9
PTXDA[9..0]
PRXDA[9 ..0]
TXCLKB
TXCLKOB
TXDB0
TXDB1
TXDB2
TXDB3
TXDB4
TXDB5
TXDB6
TXDB7
TXCTB0
TXCTB1
TXDB[7.. 0]
TXCTB[1..0]
RXCLK B+
RXCLK B-
RXDB0
RXDB1
RXDB2
RXDB3
RXDB4
RXDB5
RXDB6
RXDB7
RXSTB0
RXSTB1
RXDB[7..0]
RXSTB[2..0]
PTXDB0
PTXDB1
PTXDB2
PTXDB3
PTXDB4
PTXDB5
PTXDB6
PTXDB7
PTXDB8
PTXDB9
PRXDB0
PRXDB1
PRXDB2
PRXDB3
PRXDB4
PRXDB5
PRXDB6
PRXDB7
PRXDB8
PRXDB9
PTXDB[9..0]
PRXDB[9 ..0]
PA7/*FLAGD /SLCS#
C20
0.1 u
C21
0.1 u
C10
0.1 u
C11
0.1 u
C12
0.1 u
C13
0.1 u
C14
0.1 u
C15
0.1 u
C16
0.1 u
C17
0.1 u
C18
0.1 u
C19
0.1 u
+3.3V +1.5V
C9
0.1 u
+3.3V
RESET#
RXSTB2
RXSTA 2
RC L KENA
RCLKE NB
SPDSELA
SPDSELB
LPENA
INSELA
INS ELB
ULCA
ULCB
LDTDEN
1
2
3
JB1
3PIN
1
2
3
JB2
3PIN
R1
0
R2
0
+3.3 V
+3.3 V
SPDSE LA'
SPDSE LB'
SPDSELB'
SPDSELA'
PTXCLKA
PTXCLKB
PRXCLKA
PRXCLKB
FD[15..0 ]
CTL[2..0]
RDY[1.. 0]
FD[1 5..0 ]
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
FD8
FD9
FD10
FD11
FD12
FD13
FD14
FD15
CTL[2. .0] CTL0
CTL1
CTL2
RDY[1.. 0]
RDY0
RDY1
F1CONFIG_DONE
F1nSTATUS
CD/MUTEB2
TCK
TDI
TMS
TDO
+1.5VA
+1.5V
+1.5V
C146
0.1 u
C147
1n
+1.5VA
C148
0.1 u
C149
1n
C143
0.1 u
C155
0.1 u
D11
LED2
D12
LED2
D13
LED2
D14
LED2
D9
LED2
D10
LED2
D5
LED2
D6
LED2
D7
LED2
D8
LED2
D3
LED2
D4
LED2
R174
22 1
R175
22 1
R176
22 1
R177
22 1
R178
22 1
R179
22 1
R168
22 1
R169
22 1
R170
22 1
R171
22 1
R172
22 1
R173
22 1
LFIA
CDA
L27 0A
L36 0A
L54 0A
L74 25A
LFIB
CDB
L27 0B
L36 0B
L54 0B
L74 25B
LFIA
CDA
L27 0A
L36 0A
L54 0A
L7425A
LFIB
CDB
L27 0B
L36 0B
L54 0B
L7425B
D30
LED2
R196
221
+3.3 V
LPENB
C172
0.1 u
C173
0.1 u
C174
0.1 u
C175
0.1 u
C176
0.1 u
C177
0.1 u
C178
0.1 u
C179
0.1 u
C180
0.1 u
C181
0.1 u
C182
0.1 u
C183
0.1 u
+3.3V +1.5V
C171
0.1 u
C170
0.1 u
TXERRA
TXERRB
FCLKA+
FCLKA-
FCLKB +
FCLKB -
R213
0
R214
0
rxstb[2]
C3
txda[1 ]
C2
rxda [3]
D3
lpenb
D2
scl
D4
txclka
D1
inselb
E3
txcta[1]
E2
RESERVED_INPUT
F1
rxda [7]
E4
RESERVED_INPUT
E5
sdo
F2
scse
F3
lfia
F4
RESERVED_INPUT
F5
RESERVED_INPUT
G1
RESERVED_INPUT
G2
RESERVED_INPUT
F6
RESERVED_INPUT
F7
RESERVED_INPUT
H6
RESERVED_INPUT
J1
DATA0
H7
nCONFIG
J2
VCCA_PLL1
J5
rxclka_p
J3
txcl koa
J4
GNDA_ PLL1
K1
GNDG_ PLL1
J6
nCEO
K2
nCE
J7
MSEL 0
K3
MSEL 1
K7
DCL K
L1
RESERVED_INPUT
K6
fcl ka_ p
K4
fcl ka_ n
K5
fd [ 8]
M4
fd [ 7]
N1
fd [ 6]
N2
RESERVED_INPUT
M6
RESERVED_INPUT
N7
RESERVED_INPUT
N5
RESERVED_INPUT
N6
fd[ 11]
N3
fd[ 10]
N4
RESERVED_INPUT
P5
fd[ 12]
P2
fd[ 13]
P3
fd [ 5]
R1
RESERVED_INPUT
P4
fd [ 4]
R2
fd[ 14]
R3
fd[ 15]
T2
clkou t
T3
BANK1
RESERVED_INPUT
G3
RESERVED_INPUT
G4
RESERVED_INPUT
G5
RESERVED_INPUT
G6
RESERVED_INPUT
H1
RESERVED_INPUT
H2
rxclka_n
H3
sdi
H4
RESERVED_INPUT
H5
RESERVED_INPUT
L7
RESERVED_INPUT
L6
ctl[2]
L2
reset_n
L3
RESERVED_INPUT
L5
pa7_ fl agd_ slcs
L4
ctl[1]
M1
fd [ 9]
M3
ctl[0]
M2
RESERVED_INPUT
M5
U2A
EP1C20F32 4C8
rxstb[ 1]
C16
txerrb
B16
VCCINT
G11
GND
F11
rxstb[ 0]
B15
spd selb
A15
lp en a
C15
rclkena
D14
txd b[ 3]
B14
rxdb[4]
C14
RESE RVE D _INPUT
E13
GND
G10
VCCINT
F10
rxdb[5]
C11
rxsta[1]
D11
txd b[ 0]
B11
txct b[ 1]
A11
RESE RVE D _INPUT
C10
rxda[ 2]
D10
RESE RVE D _INPUT
E10
rxdb[2]
C8
txd a[7 ]
A8
txd a[4 ]
B8
RESE RVE D _INPUT
E8
RESE RVE D _INPUT
E7
txd a[5 ]
A7
txd a[6 ]
B7
lfib
C7
RESE RVE D _INPUT
E6
rxda[ 4]
D6
txd a[3 ]
B6
rxdb[7]
C6
txd a[0 ]
A6
RESE RVE D _INPUT
B5
rxdb[3]
C5
rxda[ 5]
D5
txd a[2 ]
A4
rxdb[6]
B4
VCCINT
F8
GND
G8
txerra
B3
rxda[ 6]
C4
BANK2
txd b[ 2]
B13
txcl kb
A13
ins el a
D13
rxdb[1]
C13
rxsta[2]
D12
rxdb[0]
C12
txd b[ 7]
B12
txd b[ 4]
A12
txd b[ 1]
B10
txd b[ 5]
A10
VCCINT
G9
GND
F9
rxsta[0]
D9
RESE RVE D _INPUT
C9
txct a[0]
A9
txct b[ 0]
B9
rxda[ 0]
D8
rxda[ 1]
D7
RESE RVE D _INPUT
E11
U2B
EP1C20F32 4C 8
led2
T16
ledcdb
T17
ptxda [ 1]
R17
ptxda [ 0]
R18
prxclkb
R15
ledl fi b
R16
led2 70b
P16
led3 60b
P17
RESE RVE D _INPUT
P15
RESE RVE D _INPUT
P14
RESE RVE D _INPUT
N14
led5 40b
N18
ptxcl ka
N17
RESE RVE D _INPUT
N13
RESE RVE D _INPUT
N12
led7 425 b
N16
RESE RVE D _INPUT
N15
ledl fi a
M1 8
ledcda
M1 7
fclkb_p
K16
fclkb_n
K15
CONF_DONE
K17
nSTATU S
L12
TCK
K18
TMS
K14
TDO
K13
GNDG_PLL2
J18
GNDA_PLL2
K12
txcl kob
J16
rxc lkb_p
J15
VCCA_PLL2
J12
TDI
J17
RESE RVE D _INPUT
J14
RESE RVE D _INPUT
G13
RESE RVE D _INPUT
G14
RESE RVE D _INPUT
G15
RESE RVE D _INPUT
G16
RESE RVE D _INPUT
G12
RESE RVE D _INPUT
F12
cd_muteb
F18
sd_hdb
F17
RESE RVE D _INPUT
F13
RESE RVE D _INPUT
F14
cd_muteb2
F16
RESE RVE D _INPUT
F15
RESE RVE D _INPUT
E17
rclkenb
E16
ulca
E15
spd sela
D18
RESE RVE D _INPUT
E14
ld td en
D16
RESE RVE D _INPUT
D15
txd b[ 6]
C17
ulcb
D17
BANK3
RESE RVE D _INPUT
M1 4
RESE RVE D _INPUT
M1 5
led2 70a
M1 6
led5 40a
L18
led3 60a
L17
RESE RVE D _INPUT
M1 3
RESE RVE D _INPUT
L13
led7 425 a
L16
RESE RVE D _INPUT
L15
RESE RVE D _INPUT
L14
RESE RVE D _INPUT
J13
RESE RVE D _INPUT
H13
RESE RVE D _INPUT
H14
rxc lkb_n
H15
RESE RVE D _INPUT
H16
RESE RVE D _INPUT
H17
cd_mutea
H18
sd_hda
G18
RESE RVE D _INPUT
G17
U2C
EP1C20F32 4C 8
rdy[1]
U3
fd [2 ]
V4
VCCINT
M8
GND
N8
ifcl k
T4
fd [3 ]
U4
pt xdb[9]
T5
prxda [9]
U5
rdy[0]
R4
prxdb [9 ]
R5
fd [0 ]
V6
fd [1 ]
U6
RES ERVED_INPUT
P6
RES ERVED_INPUT
P7
pt xdb[8]
T6
prxda [8]
U7
pt xda[9]
V7
pt xdb[7]
T7
prxdb [7 ]
R7
prxda [7]
U8
pt xda[8]
V8
pt xdb[6]
T8
RES ERVED_INPUT
P9
pt xdb[4]
T10
prxdb [4 ]
R10
prxdb [3 ]
R11
pt xdb[3]
T11
prxda [4]
U11
pt xda[5]
V11
GND
N10
VCCINT
M1 0
RES ERVED_INPUT
P12
RES ERVED_INPUT
P13
prxda [1]
U14
pt xdb[0]
T14
prxdb [0 ]
R14
pt xda[2]
V15
prxda [0]
U15
VCCINT
N11
GND
M1 1
prxc lka
U16
pt xclkb
T15
BANK4
prxdb [8 ]
R6
prxda [6]
U9
pt xda[7]
V9
prxdb [5 ]
R9
pt xdb[5]
T9
GND
M9
VCCINT
N9
prxda [5]
U10
pt xda[6]
V10
RES ERVED_INPUT
P10
pt xda[4]
V12
prxda [3]
U12
pt xdb[2]
T12
prxdb [2 ]
R12
pt xda[3]
V13
prxda [2]
U13
pt xdb[1]
T13
prxdb [1 ]
R13
prxdb [6 ]
R8
U2D
EP1C20F 32 4C8
VC CI NT
A17
VC CI NT
A2
VC CI NT
B1
VC CI NT
B18
VC CI NT
H10
VC CI NT
J9
VC CI NT
K10
VC CI NT
L9
VC CI NT
U1
VC CI NT
U18
VC CI NT
V17
VC CI NT
V2
VC C I O1
E1
VC C I O1
G7
VC C I O1
M7
VC C I O1
P1
VC C I O2
A14
VC C I O2
A5
VC C I O2
E12
VC C I O2
E9
VC C I O3
E18
VC C I O3
H12
VC C I O3
M12
VC C I O3
P18
VC C I O4
P11
VC C I O4
P8
VC C I O4
V14
VC C I O4
V5
GN D
A1
GN D
A1 6
GN D
A1 8
GN D
A3
GN D
B17
GN D
B2
GN D
C1
GN D
C18
GN D
H1 1
GN D
H8
GN D
H9
GN D
J10
GN D
J11
GN D
J8
GN D
K1 1
GN D
K8
GN D
K9
GN D
L10
GN D
L11
GN D
L8
GN D
T1
GN D
T18
GN D
U1 7
GN D
U2
GN D
V1
GN D
V1 6
GN D
V1 8
GN D
V3
POWER/GND
U2E
EP1C20F32 4C 8
+
C250
10 u
+3.3V
[+] Feedback
- Quad Independent Channel 1
- HOTLink II™ CYV15G0404DXB 1
- Video PHY Demonstration Board 1
- Users Guide 1
- Page 2 of 92 2
- Page 3 of 92 3
- LIST OF TABLES 4
- 1.0 Introduction 5
- 2.0 Kit Contents 5
- 3.0 Demo Board Features 6
- 4.0 Board Architecture 7
- 4.2 Clocking Architecture 8
- Programmable 10
- 4.4 Power Supply 11
- 5.0 GUI and Operating Modes 12
- [+] Feedback 13
- 5.1 Setting the SDI Data Rate 14
- 5.3 Standard 15
- 5.4 Transmit Test Pattern 16
- 5.5 Status 16
- 6.0 Sample Test Procedures 17
- 6.3 Tests 19
- Page 23 of 92 23
- Page 24 of 92 24
- Page 27 of 92 27
- Page 28 of 92 28
- 7.0 Summary 29
- 8.0 References 29
- Linear Syst ems Ltd 33
- Page 36 of 92 36
- Page 38 of 92 38
- (GERBER Files) 43
- Page 45 of 92 45
- Figure B-2. Top Overlay 45
- Page 64 of 92 64
- (Drill and Assembly) 65
- Page 66 of 92 66
- Figure C-1. Drill Placement 66
- Page 67 of 92 67
- Figure C-2. Assembly–Top View 67
- Page 68 of 92 68
- Video Demo Board 69
- Setting Configurations 85
- SD-SDI to HD-SDI Upconversion 86
- Channel B 87
- Channel A 87
- FPGA (U2) 87
- Board Modification 88
- FPGA(U2) 89
- PLL 1 PLL 2 JP11 89
- Page 91 of 92 91
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