Cypress Semiconductor STK22C48 Manual de usuario descargar pdf (Pagina 10)

STK22C48

Document Number: 001-51000 Rev. *E Page 10 of 17

SRAM Write Cycle

Parameter

Description

25 ns 45 ns

Unit

Min Max Min Max

Cypress

Parameter

Alt

AVAV

Write cycle time 25 – 45 – ns

PWE

WLWH,

WLEH

Write pulse width 20 – 30 – ns

SCE

ELWH,

ELEH

Chip enable to end of write 20 – 30 – ns

DVWH,

DVEH

Data setup to end of write 10 – 15 – ns

WHDX,

EHDX

Data hold after end of write 0 – 0 – ns

AVWH,

AVEH

Address setup to end of write 20 – 30 – ns

AVWL,

AVEL

Address setup to start of write 0 – 0 – ns

WHAX,

EHAX

Address hold after end of write 0 – 0 – ns

HZWE

[10, 11]

WLQZ

Write enable to output disable – 10 – 14 ns

LZWE

[10]

WHQX

Output active after end of write 5 – 5 – ns

Switching Waveforms

Figure 9. SRAM Write Cycle 1: WE Controlled

[12, 13]

Figure 10. SRAM Write Cycle 2: CE Controlled

[12, 13]

SCE

PWE

HZWE

LZWE

ADDRESS

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

ADDRESS

SCE

PWE

DATA IN

DATA OUT

HIGH IMPEDANCE

DATA VALID

Notes

10. Measured ±200 mV from steady state output voltage.

11. If WE

is Low when CE goes Low, the outputs remain in the high impedance state.

12. HSB

must be high during SRAM Write cycles.

13.

or WE must be greater than V

during address transitions.

Not Recommended for New Designs. In production to support ongoing production programs only.

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