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Cypress Semiconductor NoBL CY7C1464AV25 Manual de usuario Pagina 1

Busca en linea o descarga Manual de usuario para No Cypress Semiconductor NoBL CY7C1464AV25. Cypress Semiconductor CY7C1462AV25-200AXC Manual de usuario

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36-Mbit (1M x 36/2M x 18/512K x 72)
Pipelined SRAM with NoBL™ Architecture
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05354 Rev. *D Revised June 22, 2006
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous
OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• 2.5V core power supply
• 2.5V/1.8V I/O power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN
) pin to suspend operation
• Synchronous self-timed writes
• CY7C1460AV25, CY7C1462AV25 available in
JEDEC-standard lead-free 100-pin TQFP package,
lead-free and non-lead-free 165-ball FBGA package.
CY7C1464AV25 available in lead-free and non-lead-free
209-ball FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back
Read/Write operations with no wait states. The
CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The
CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Write operations are controlled by the
Byte Write Selects (BW
a
–BW
h
for CY7C1464AV25,
BW
a
–BW
d
for CY7C1460AV25 and BW
a
–BW
b
for
CY7C1462AV25) and a Write Enable (WE
) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE
) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
A0, A1, A
C
MODE
BW
a
BW
b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
a
DQP
b
DQP
c
DQP
d
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
C
EN
WRITE
DRIVERS
BW
c
BW
d
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
Logic Block Diagram–CY7C1460AV25 (1M x 36)
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Indice de contenidos

Pagina 1 - CY7C1464AV25

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ ArchitectureCY7C1460AV25CY7C1462AV25CY7C1464AV25Cypress Semiconductor Corporation • 19

Pagina 2

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 10 of 27IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1460AV25/CY7C1462AV25/CY

Pagina 3

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 11 of 27When the TAP controller is in the Capture-IR state, the twoleast signif

Pagina 4

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 12 of 27When this scan cell, called the “extest output bus tri-state,” islatche

Pagina 5

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 13 of 272.5V TAP AC Test ConditionsInput pulse levels ...

Pagina 6

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 14 of 27Scan Register SizesRegister Name Bit Size (x36) Bit Size (x18) Bit Size

Pagina 7

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 15 of 27165-ball FBGA Boundary Scan Order[12]CY7C1460AV25 (1M x 36), CY7C1462AV

Pagina 8

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 16 of 27209-ball FBGA Boundary Scan Order[12, 13]CY7C1464AV25 (512K x 72)Bit# B

Pagina 9

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 17 of 27Maximum Ratings (Above which the useful life may be impaired. For user

Pagina 10 - [+] Feedback [+] Feedback

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 18 of 27Capacitance[16]Parameter Description Test Conditions100 TQFP Max.165 FB

Pagina 11

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 19 of 27Switching Characteristics Over the Operating Range[21, 22]Parameter Des

Pagina 12

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 2 of 27 Selection Guide250 MHz 200 MHz 167 MHz UnitMaximum Access Time 2.6 3.2

Pagina 13

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 20 of 27Switching WaveformsRead/Write/Timing[23, 24, 25]NOP, STALL and DESELECT

Pagina 14

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 21 of 27ZZ Mode Timing[27, 28]Notes: 27. Device must be deselected when enterin

Pagina 15

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 22 of 27Ordering InformationNot all of the speed, package and temperature range

Pagina 16

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 23 of 27250 CY7C1460AV25-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x

Pagina 17

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 24 of 27Package DiagramsNOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION DO

Pagina 18

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 25 of 27Package Diagrams (continued)A1PIN 1 CORNER17.00±0.1015.00±0.107.001.00Ø

Pagina 19

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 26 of 27© Cypress Semiconductor Corporation, 2006. The information contained he

Pagina 20

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 27 of 27Document History PageDocument Title: CY7C1460AV25/CY7C1462AV25/CY7C1464

Pagina 21

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 3 of 27Pin ConfigurationsAAAAA1A0VSSVDDAAAAAAVDDQVSSDQb DQb DQb VSSVDDQDQb DQb

Pagina 22

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 4 of 27Pin Configurations (continued)234 5671ABCDEFGHJKLMNPRTDONC/576MNC/1GDQPc

Pagina 23

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 5 of 27Pin Configurations (continued)ABCDEFGHJKLMNPRTUVW123456789 1110DQgDQgDQg

Pagina 24

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 6 of 27CE1Input-SynchronousChip Enable 1 Input, active LOW. Sampled on the risi

Pagina 25

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 7 of 27Functional OverviewThe CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 aresynchro

Pagina 26

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 8 of 27CY7C1460AV25, BWa,b,c,d for CY7C1460AV25 and BWa,b forCY7C1462AV25) inpu

Pagina 27

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 9 of 27Partial Write Cycle Description[1, 2, 3, 8]Function (CY7C1460AV25) WE BW

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