CY7C603xx
Document #: 38-16018 Rev. *D Page 3 of 29
normal operating voltages off a single battery cell, and various
system resets supported by the M8C.
The Digital System
The Digital System is composed of 4 digital enCoRe III LV
blocks. Each block is an 8-bit resource. Digital peripheral
configurations include those listed below.
• PWM usable as Timer/Counter
• SPI master and slave
• I2C slave and multi-master
•CMP
•ADC10
• SARADC
Figure 2. Digital System Block Diagram
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing
logic operations. This configurability frees your designs from
the constraints of a fixed peripheral controller.
The Analog System
The Analog System is composed of two configurable blocks.
Analog peripherals are very flexible and can be customized to
support specific application requirements. Some of the
common analog functions for this device (most available as
user modules) are listed below.
• Analog-to-digital converters (single with 8-bit resolution)
• Pin-to-pin comparators
• Single-ended comparators with absolute (1.3V) reference
• 1.3V reference (as a System Resource)
Analog blocks are provided in columns of two, which includes
one CT (Continuous Time - ACE00 or ACE01) and one SC
(Switched Capacitor - ASE10 or ASE11) blocks.
Figure 3. Analog System Block Diagram
The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins can
be connected to the bus individually or in any combination.
The bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. An additional
8:1 analog input multiplexer provides a second path to bring
Port 0 pins to the analog array.
Additional System Resources
System Resources, some of which have been previously
listed, provide additional capability useful to complete
systems. Additional resources include a switch mode pump,
low voltage detection, and power on reset. Brief statements
describing the merits of each system resource are presented
below.
• Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be
routed to both the digital and analog systems. Additional
clocks can be generated using digital blocks as clock
dividers.
• The I2C module provides 100- and 400-kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
• Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
DIGITAL SYSTEM
To System Bus
D
i
g
i
t
a
l
C
l
o
c
k
s
F
r
o
m
C
o
r
e
Digital enCoRe II LV Block Array
To Analog
System
8
Row Input
Configuration
Row Output
Configuration
88
8
Row 0
DBB00 DBB01 DCB02 DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 3
Port 2
Port 1
Port 0
ACOL1MUX
ACE00 ACE01
Array
Array Input
Configuration
ASE10 ASE11
X
X
X
X
X
Analog Mux Bus
All IO
ACI0[1:0] ACI1[1:0]
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