
CY7C603xx
Document #: 38-16018 Rev. *D Page 26 of 29
Figure 12. Definition for Timing for Fast/Standard Mode on the I
2
C Bus
Packaging Information
This section illustrates the packaging specifications for the CY7C603xx device, along with the thermal impedances for each
package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description
of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/support/link.cfm?mr=poddim.
Packaging Dimensions
Figure 13. 28-Lead (210-Mil) SSOP
SDA
SCL
S
Sr SP
T
BUFI2C
T
SPI2C
T
HDSTAI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
51-85079-*C
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