AN57322
November 4, 2009 Document No. 001-57322 Rev. ** 6
tRC - Read Cycle Time (min)
When IFCLK=48 MHz, each GPIF cycle is 20.83 ns.
tACE - CE/ Low to Data Valid (max)
When IFCLK=48 MHz, each GPIF cycle is 20.83 ns. Therefore, CE/ must be
driven low for one cycle in s0; sample data on the next cycle. Data is sampled on
rising edge of IFCLK entering the state.
tDOE - OE/ Low to Data Valid (max)
Data is valid worst case 5 ns after OE/ is asserted. Data is valid in the next GPIF
cycle; sample data in s1.
tHZOE - OE/ High to High-Z (max)
It is also possible to de-assert OE/ in s1 because the data is already sampled.
Data hold time is not an issue.
Now that the timing parameters involved are understood,
the read waveform can be designed in GPIF designer. The
following state flow diagram must be accomplished:
Follow these steps to complete the FIFO Read
waveform.
1. Click the FIFO Read tab
2. Right-click the left boundary of the OE/ trace and
select Low (0). Click on the OE/ trace one clock cycle
from the left boundary. This places an action point
and creates the OE/ waveform. State 0 (s0) is
generated automatically and lasts for 1 IFCLK cycle
(20.83 ns). Thus, OE/ is asserted for 20.83 ns.
3. Assert and de-assert CE/ along with OE/. To do this,
right-click on CE/ trace and select Low (0). Now, click
on the CE/ trace one clock cycle from the left
boundary
4. WE/ must be kept HIGH throughout the waveform.
From the waveform observe that WE/ is high by
default.
5. In the data trace, observe a yellow line on the data
trace. This is because GPIF Designer forces all the
four waveforms to be in the same IDLE state. Right-
click the action point on the data trace and click Same
Data. Observe that the yellow line has disappeared
even in the write waveform. Change this after
completing the read waveform.
6. The waveform should appear as follows:
7. The data bus must be sampled one clock cycle after
asserting the CE/ to ensure that data is valid before
sampling (tACE). To do this, click the data trace on
the right boundary of s0. This causes the data trace to
toggle HIGH (placing an “Activate Data” event).
8. The data bus should only be sampled for one clock
cycle. To stop sampling after one clock cycle, place
another action point on the data trace after another
clock cycle. Notice that the data trace is high for just
the duration of s1 now. The waveform should appear
as follows:
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