AN57322
November 4, 2009 Document No. 001-57322 Rev. ** 12
FIFORESET = 0x00; // clear NAKALL bit to
resume normal operation
SYNCDELAY;
EP2FIFOCFG = 0x00; // allow core to see
zero to one transition of auto out bit
SYNCDELAY;
EP2FIFOCFG = 0x10; // auto out mode,
disable PKTEND zero length send, byte ops
SYNCDELAY;
EP6FIFOCFG = 0x08; // auto in mode,
disable PKTEND zero length send, byte ops
SYNCDELAY;
// enable dual autopointer feature
AUTOPTRSETUP |= 0x01;
GpifInit (); // initialize GPIF
registers
PORTACFG = 0x00;
OEA |= 0xF3;
IOA &= 0xFC;
Rwuen = TRUE; // Enable
remote-wakeup
}
BOOL DR_SetConfiguration(void) // Called
when a Set Configuration command is
received
{
if( EZUSB_HIGHSPEED( ) )
{
// FX2 enumerated at high speed
SYNCDELAY;
EP6AUTOINLENH = 0x02; // set
AUTOIN commit length to 512 bytes
SYNCDELAY;
EP6AUTOINLENL = 0x00;
SYNCDELAY;
enum_high_speed = TRUE;
}
else
{ // FX2 enumerated at full speed
SYNCDELAY;
EP6AUTOINLENH = 0x00; // set AUTOIN
commit length to 64 bytes
SYNCDELAY;
EP6AUTOINLENL = 0x40;
SYNCDELAY;
enum_high_speed = FALSE;
}
Configuration = SETUPDAT[2];
return(TRUE); // Handled by
user code
}
void TD_Poll(void)
{
// blink LED0 to indicate firmware is
running
if (++LED_Count == 10000)
{
if (LED_Status)
{
LED_Off (bmBIT0);
LED_Status = 0;
}
else
{
LED_On (bmBIT0);
LED_Status = 1;
}
LED_Count = 0;
}
}
BOOL DR_VendorCmnd(void)
{
BYTE tmp;
switch (SETUPDAT[1])
{
case VR_NAKALL_ON:
tmp = FIFORESET;
tmp |= bmNAKALL;
SYNCDELAY;
FIFORESET = tmp;
break;
case VR_NAKALL_OFF:
tmp = FIFORESET;
tmp &= ~bmNAKALL;
SYNCDELAY;
FIFORESET = tmp;
break;
case VX_BB: // actuate write to
SRAM
{
EP0BUF[0] = VX_BB;
IOA = (IOA & 0x0F) + (SETUPDAT[3] <<
3); // select bank of 16x512 (bit shift
MSB of wValue by 3
// and OR it
with PA[7:4]
GPIFADRH = SETUPDAT[3];
// set GPIFADR[8:0] to address passed down
in wValue
GPIFADRL = SETUPDAT[2];
len = ( (SETUPDAT[5] << 8) +
SETUPDAT[4] ); // get transfer length from
wIndex field
while (len)
// while the transfer length is non-zero,
{
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