Cypress Semiconductor CY7C1399B Manual de usuario descargar pdf (Pagina 11)

AN57322

November 4, 2009 Document No. 001-57322 Rev. ** 11

Appendix A

#define VX_BB 0xBB // GPIF write

#define VX_BC 0xBC // GPIF read

#define GPIFTRIGRD 4

#define GPIF_EP2 0

#define GPIF_EP4 1

#define GPIF_EP6 2

#define GPIF_EP8 3

BOOL enum_high_speed = FALSE; // flag

to let firmware know FX2 enumerated at high

speed

static WORD xFIFOBC_IN = 0x0000; //

variable that contains EP6FIFOBCH/L value

static WORD xdata LED_Count = 0;

static BYTE xdata LED_Status = 0;

WORD addr, len, Tcount;

// ...debug LEDs: accessed via movx reads

only ( through CPLD )

// it may be worth noting here that the

default monitor loads at 0xC000

xdata volatile const BYTE LED0_ON _at_

0x8000;

xdata volatile const BYTE LED0_OFF _at_

0x8100;

xdata volatile const BYTE LED1_ON _at_

0x9000;

xdata volatile const BYTE LED1_OFF _at_

0x9100;

xdata volatile const BYTE LED2_ON _at_

0xA000;

xdata volatile const BYTE LED2_OFF _at_

0xA100;

xdata volatile const BYTE LED3_ON _at_

0xB000;

xdata volatile const BYTE LED3_OFF _at_

0xB100;

// use this global variable when

(de)asserting debug LEDs...

BYTE xdata ledX_rdvar = 0x00;

BYTE xdata LED_State = 0;

void LED_Off (BYTE LED_Mask);

void LED_On (BYTE LED_Mask);

void GpifInit ();

void LED_Off (BYTE LED_Mask)

{

if (LED_Mask & bmBIT0)

{

ledX_rdvar = LED0_OFF;

LED_State &= ~bmBIT0;

}

if (LED_Mask & bmBIT1)

{

ledX_rdvar = LED1_OFF;

LED_State &= ~bmBIT1;

}

if (LED_Mask & bmBIT2)

{

ledX_rdvar = LED2_OFF;

LED_State &= ~bmBIT2;

}

if (LED_Mask & bmBIT3)

{

ledX_rdvar = LED3_OFF;

LED_State &= ~bmBIT3;

}

}

void LED_On (BYTE LED_Mask)

{

if (LED_Mask & bmBIT0)

{

ledX_rdvar = LED0_ON;

LED_State |= bmBIT0;

}

if (LED_Mask & bmBIT1)

{

ledX_rdvar = LED1_ON;

LED_State |= bmBIT1;

}

if (LED_Mask & bmBIT2)

{

ledX_rdvar = LED2_ON;

LED_State |= bmBIT2;

}

if (LED_Mask & bmBIT3)

{

ledX_rdvar = LED3_ON;

LED_State |= bmBIT3;

}

}

void TD_Init(void) // Called

once at startup

{

// set the CPU clock to 48MHz

CPUCS = ((CPUCS & ~bmCLKSPD) |

bmCLKSPD1) ;

SYNCDELAY;

// set the slave FIFO interface to 48MHz

IFCONFIG |= 0x40;

//change EP configuration

EP2CFG = 0xA0;

SYNCDELAY;

EP4CFG = 0x00;

SYNCDELAY;

EP6CFG = 0xE0;

SYNCDELAY;

EP8CFG = 0x00;

// out endpoints do not come up armed

FIFORESET = 0x80; // set NAKALL bit to

NAK all transfers from host

SYNCDELAY;

FIFORESET = 0x02; // reset EP2 FIFO

SYNCDELAY;

FIFORESET = 0x06; // reset EP6 FIFO

SYNCDELAY;

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