Cypress Semiconductor CY7C1383D Manual de usuario descargar pdf (Pagina 21)

CY7C1381D

CY7C1383D

Document #: 38-05544 Rev. *C Page 21 of 29

Switching Characteristics Over the Operating Range

[23, 24]

Parameter Description

133 MHz 100 MHz

UnitMin. Max. Min. Max.

POWER

(Typical) to the first Access

[19]

11ms

Clock

CYC

Clock Cycle Time 7.5 10 ns

Clock HIGH 2.1 2.5 ns

Clock LOW 2.1 2.5 ns

Output Times

CDV

Data Output Valid After CLK Rise 6.5 8.5 ns

DOH

Data Output Hold After CLK Rise 2.0 2.0 ns

CLZ

Clock to Low-Z

[20, 21, 22]

2.0 2.0 ns

CHZ

Clock to High-Z

[20, 21, 22]

0 4.0 0 5.0 ns

OEV

OE LOW to Output Valid 3.2 3.8 ns

OELZ

OE LOW to Output Low-Z

[20, 21, 22]

00ns

OEHZ

OE HIGH to Output High-Z

[20, 21, 22]

4.0 5.0 ns

Set-up Times

Address Set-up Before CLK Rise 1.5 1.5 ns

ADS

ADSP, ADSC Set-up Before CLK Rise 1.5 1.5 ns

ADVS

ADV Set-up Before CLK Rise 1.5 1.5 ns

WES

GW, BWE, BW

[A:D]

Set-up Before CLK Rise 1.5 1.5 ns

Data Input Set-up Before CLK Rise 1.5 1.5 ns

CES

Chip Enable Set-up 1.5 1.5 ns

Hold Times

Address Hold After CLK Rise 0.5 0.5 ns

ADH

ADSP, ADSC Hold After CLK Rise 0.5 0.5 ns

WEH

BWE

[A:D]

Hold After CLK Rise

0.5 0.5 ns

ADVH

ADV Hold After CLK Rise 0.5 0.5 ns

Data Input Hold After CLK Rise 0.5 0.5 ns

CEH

Chip Enable Hold After CLK Rise 0.5 0.5 ns

Notes:

18.Tested initially and after any design or process change that may affect these parameters.

19.This part has a voltage regulator internally; t

POWER

is the time that the power needs to be supplied above V

(minimum) initially, before a read or write operation

can be initiated.

20.t

CHZ

, t

CLZ

OELZ

, and t

OEHZ

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

21.At any given voltage and temperature, t

OEHZ

is less than t

OELZ

and t

CHZ

is less than t

CLZ

to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system condition.

22.This parameter is sampled and not 100% tested.

23.Timing reference level is 1.5V when V

DDQ

= 3.3V and is 1.25V when V

DDQ

= 2.5V.

24.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Comentarios a estos manuales

Sin comentarios

Cypress Semiconductor CY7C1383D Manual de usuario Pagina 21

Comentarios a estos manuales

Relacionado con productos y manuales para No Cypress Semiconductor CY7C1383D