Cypress Semiconductor CY7C1364C Manual de usuario descargar pdf (Pagina 28)

CY7C1364C

Document Number: 001-74592 Rev. *B Page 28 of 29

Document History Page

Document Title: CY7C1364C, 9-Mbit (256 K × 32) Pipelined Sync SRAM

Document Number: 001-74592

Rev. ECN No. Issue Date

Orig. of

Change

Description of Change

** 3489597 01/10/2012 PRIT New data sheet.

*A 3508648 01/25/2012 PRIT Changed status from Preliminary to Final.

*B 3537338 02/28/2012 PRIT Added JTAG information (Updated the section Pin Definitions and added the

sections IEEE 1149.1 Serial Boundary Scan (JTAG), TAP Controller State

Diagram, TAP Controller Block Diagram, TAP Timing, TAP AC Switching

Characteristics, 3.3 V TAP AC Test Conditions, 3.3 V TAP AC Output Load

Equivalent, 2.5 V TAP AC Test Conditions, 2.5 V TAP AC Output Load

Equivalent, TAP DC Electrical Characteristics and Operating Conditions,

Identification Register Definitions, Scan Register Sizes, Instruction Codes, and

Boundary Scan Order).

1 2 ... 23 24 25 26 27 28 29 30

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Cypress Semiconductor CY7C1364C Manual de usuario Pagina 28