Cypress Semiconductor CY7C1364C Manual de usuario descargar pdf (Pagina 23)

CY7C1364C

Document Number: 001-74592 Rev. *B Page 23 of 29

Figure 5. Read/Write Cycle Timing

[24, 25, 26]

Switching Waveforms (continued)

CYC

CLK

ADSP

ADH

ADS

ADDRESS

ADSC

CEH

CES

BWE,

BW[A:D]

Data Out (Q)

High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READBack-to-Back READs

High-Z

Q(A2)Q(A1)

Q(A4) Q(A4+1) Q(A4+2)

WEH

WES

Q(A4+3)

OEHZ

OELZ

CLZ

Back-to-Back

WRITEs

DON’T CARE UNDEFINED

Notes

24. On this diagram, when CE

is LOW, CE

is HIGH and CE

is LOW. When CE is HIGH, CE

is HIGH or CE

is LOW or CE

is HIGH.

25. The data bus (Q) remains in High Z following a Write cycle unless an ADSP

, ADSC, or ADV cycle is performed.

26. GW

is HIGH.

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 29 30

CY7C1364C 1
Single Read Accesses 6
Disabling the JTAG Feature 10
Test Access Port (TAP) 10
Performing a TAP Reset 10
TAP Registers 10
TAP Instruction Set 10
Ordering Code Definitions 25
Units of Measure 27
PSoC Solutions 29
Products 29
Mouser Electronics 30

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