
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
25
Read/Write Cycle Timing
[15, 16, 17]
Switching Waveforms
(continued)
ADSP
CLK
ADSC
ADV
ADD
CE
1
OE
GW
WE
CE
2
CE
3
1a
Data In/Out
t
CYC
t
CH
t
CL
t
ADS
t
ADH
t
ADS
t
ADH
t
ADVS
t
ADVH
RD1
WD2
RD3
t
AH
t
AS
t
WS
t
WH
t
WH
t
WS
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
t
EOLZ
t
CO
t
EOV
3a
3c
3d
1a
t
EOHZ
t
DOH
t
CHZ
Single Read
Burst Read
Unselected
ADSP ignored with CE
1
inactive
CE
1
masks ADSP
= DON’T CARE
= UNDEFINED
Pipelined Read
Out
2a
In
3b
Out
Out
Out Out
Single Write
t
DS
t
DH
2a
Out
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