Cypress Semiconductor CY7C1364C Manual de usuario Pagina 1

PRELIMINARY 256K x 36/256K x 32/512K x 18 Pipelined SRAM CY7C1360V25CY7C1362V25CY7C1364V25Cypress Semiconductor Corporation• 3901 North First Street

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY10Cycle Description[1, 2, 3]Next Cycle Add. Used ZZ CE3CE2CE1ADSP ADSC ADV OE DQ WriteUnselected None L X

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY11Write Cycle Description[1, 2, 3]Function (1360/1364) GW BWE BWdBWcBWbBWaRead 11XXXXRead 101111Write Byte

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY12IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1360/62 incorporates a serial boundary scan TestAccess Po

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY13SRAM and cannot preload the Input or Output buffers. TheSRAM does not implement the 1149.1 commands EXTE

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY14TAP Controller State DiagramTEST-LOGICRESETTEST-LOGIC/IDLESELECTDR-SCANCAPTURE-DRSHIFT-DREXIT1-DRPAUSE-D

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY15TAP Controller Block Diagram0012..293031Boundary Scan RegisterIdentification Register012...x012Instruct

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY16TAP AC Switching Characteristics Over the Operating Range[6, 7]Parameters Description Min. Max. UnittTCY

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY17TAP Timing and Test Conditions(a)TDOCL=20 pFZ0=50ΩGND1.25VTest ClockTest Mode SelectTCKTMSTest Data-InTD

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY18Identification Register DefinitionsInstruction Field Value DescriptionRevision Number(31:28)TBD Reserved

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY19Boundary Scan OrderBit #Signal NameBump IDBit #Signal NameBump ID1 TBD TBD 36 TBD TBD2 TBD TBD 37 TBD TB

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY2Pin ConfigurationsAAAAA1A0DNUDNUVSSVDDDNUAAAAAAAANC,DQPbDQbDQbVDDQVSSQDQbDQbDQbDQbVSSQVDDQDQbDQbVSSNCVDDZ

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY20Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Storage T

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY21Capacitance[10]Parameter Description Test Conditions Max. UnitCIN Input Capacitance TA = 25°C, f = 1 M

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY22Switching Characteristics Over the Operating Range[12, 13, 14]-200 -166 -133 -100Parameter DescriptionMi

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY231Switching Waveforms Write Cycle Timing[15, 16]Notes:15. WE is the combination of BWE, BWx, and GW to de

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY24Read Cycle Timing[15, 17]Note:17. RDx stands for Read Data from Address X.Switching Waveforms (continue

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY25Read/Write Cycle Timing[15, 16, 17]Switching Waveforms (continued)ADSPCLKADSCADVADDCE1OEGWWECE2CE31aDat

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY26Notes:18. Device originally deselected.19. CE is the combination of CE2 and CE3. All chip selects need t

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY27Switching Waveforms (continued)OEThree-StateI/OstEOHZtEOVtEOLZOE Switching Waveforms

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY28Switching Waveforms (continued)ADSPCLKADSCCE1CE3 LOW HIGHZZtZZStZZRECIDDIDD(active)Three-stateI/O’sNote

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY29Ordering InformationSpeed(MHz)Ordering CodePackageNamePackage TypeOperatingRange200 CY7C1360V25-200AC A1

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY3Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDDQNCNCNC,DQPcDQcDQdDQcDQdAA AAADSP VDDQCE2ADQcVDD

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY30Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A10151-85050-A

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY4Selection Guide7C1360V25-2007C1364V25-2007C1362V25-2007C1360V25-1667C1364V25-1667C1362V25-1667C1360V25-13

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY585 85 ADSC Input-SynchronousAddress Strobe from Controller, sampled on the ris-ing edge of CLK. When asse

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY6Pin Definitions (119-Ball BGA) x18 Pin Locations x36 Pin Locations Name I/O Description4P, 4N, 2A, 3A, 5A

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY73R 3R MODE Input-StaticSelects Burst Order. When tied to GND selects lin-ear burst sequence. When tied to

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY8IntroductionFunctional OverviewAll synchronous inputs pass through input registers controlledby the risin

CY7C1360V25CY7C1362V25CY7C1364V25PRELIMINARY9Asserting ADV LOW at clock rise will automatically incrementthe burst counter to the next address in the