Cypress Semiconductor CY7C1354CV25 Manual de usuario descargar pdf (Pagina 16)

CY7C1354CV25

CY7C1356CV25

Document Number: 38-05537 Rev. *M Page 16 of 33

2.5 V TAP AC Test Conditions

Input pulse levels ...............................................V

to 2.5 V

Input rise and fall time ....................................................1 ns

Input timing reference levels ....................................... 1.25 V

Output reference levels .............................................. 1.25 V

Test load termination supply voltage .................. ........1.25 V

2.5 V TAP AC Output Load Equivalent

TAP AC Switching Characteristics

Over the Operating Range

Parameter

[14, 15]

Description Min Max Unit

Clock

TCYC

TCK clock cycle time 50 – ns

TCK clock frequency – 20 MHz

TCK clock HIGH time 20 – ns

TCK clock LOW time 20 – ns

Output Times

TDOV

TCK clock LOW to TDO valid – 10 ns

TDOX

TCK clock LOW to TDO invalid 0 – ns

Set-up Times

TMSS

TMS set-up to TCK clock rise 5 – ns

TDIS

TDI set-up to TCK clock rise 5 – ns

Capture set-up to TCK rise 5 – ns

Hold Times

TMSH

TMS hold after TCK clock rise 5 – ns

TDIH

TDI hold after clock rise 5 – ns

Capture hold after clock rise 5 – ns

TDO

1.25V

20pF

Z = 50

50

Notes

14. t

and t

refer to the set-up and hold time requirements of latching data from the boundary scan register.

15. Test conditions are specified using the load in TAP AC test Conditions. t

= 1 ns.

1 2 ... 11 12 13 14 15 16 17 18 19 20 21 ... 32 33

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Cypress Semiconductor CY7C1354CV25 Manual de usuario Pagina 16

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