Cypress Semiconductor CY7C1354CV25 Manual de usuario descargar pdf (Pagina 10)

CY7C1354CV25

CY7C1356CV25

Document Number: 38-05537 Rev. *M Page 10 of 33

Truth Table

The truth table for CY7C1354CV25/CY7C1356CV25 follows.

[2, 3, 4, 5, 6, 7, 8]

Operation Address used CE ZZ ADV/LD WE BW

OE CEN CLK DQ

Deselect cycle None H L L X X X L L–H Tri-state

Continue deselect cycle None X L H X X X L L–H Tri-state

Read cycle (begin burst) External L L L H X L L L–H Data out (Q)

Read cycle (continue burst) Next X L H X X L L L–H Data out (Q)

NOP/dummy read (begin burst) External L L L H X H L L–H Tri-state

Dummy read (continue burst) Next X L H X X H L L–H Tri-state

Write cycle (begin burst) External L L L L L X L L–H Data in (D)

Write cycle (continue burst) Next X L H X L X L L–H Data in (D)

NOP/write abort (begin burst) None L L L L H X L L–H Tri-state

Write abort (continue burst) Next X L H X H X L L–H Tri-state

Ignore clock edge (stall) Current X L X X X X H L–H –

Sleep mode None XH X XXXX X Tri-state

Notes

2. X = “Don’t Care”, H = Logic HIGH, L = Logic LOW, CE

stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = Valid signifies

that the desired byte write selects are asserted, see Write Cycle Description table for details.

3. Write is defined by WE

and BW

. See Write Cycle Description table for details.

4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

5. The DQ and DQP pins are controlled by the current cycle and the OE

signal.

6. CEN

= H inserts wait states.

7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE

8. OE

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP

= tri-state when OE is

inactive or when the device is deselected, and DQs = data when OE

is active.

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