Cypress Semiconductor Perform CY7C1372D Guía de usuario descargar pdf (Pagina 92)

Port Direction Function

Reset In System reset.

dsp_aeclk_i In DSP EMIF A clock input.

dsp_beclk_i In DSP EMIF B clock input.

ref_clk_i In Reference clock input.

pll_i_p/pll_i_n In PLL differential input clock pair. IO standard is PECL.

adc_clk In ADC clock input from the PCI controller (Spartan) clock

selection matrix.

dac_clk In DAC clock input from the PCI controller (Spartan) clock

selection matrix.

d_clk Out System clock. In the example logic this is a phase-

locked version of dsp_aeclk_i.

ref_clk Out Reference clock output. Nominally 10 Mhz for Quixote.

pll_clk2 Out The PLL clock divided by two.

dsp_aeclk Out Phase locked DSP EMIF A clock.

dsp_beclk Out Phase locked DSP EMIF B clock.

dsp_beclk_div2 Out Phase locked DSP EMIF B clock divided by two. Used

by the PCI controller interface.

dsp_a_locked Out Status flag indicating that the DSP EMIF A clock DCM is

locked.

dsp_b_locked Out Status flag indicating that the DSP EMIF A clock DCM is

locked.

adc_fs Out ADC clock input after a BUFG.

dac_fs Out DAC clock input after a BUFG.

Table 19: ii_quixote_clocks Component Ports

Target Devices : Xilinx XC2V2000-4FF896C or XC2V6000-4FF1156

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Cypress Semiconductor Perform CY7C1372D Guía de usuario Pagina 92