Cypress Semiconductor Perform CY7C1372D Guía de usuario descargar pdf (Pagina 81)

Port Direction Function

reset In Global reset for the component

d_clk In The system clock for the system interface.

d_ce In System clock enable.

fs In Sample clock

dsp_aeclk In DSP EMIF A clock, 100 Mhz nominally.

dsp_a_din[63:0] In DSP EMIF A data in

dsp_a_dout[63:0] Out DSP EMIF A data out

dsp_a_ea[22:16] In DSP EMIF A address bits 22..16

dsp_a_ce_n[1:0] In DSP EMIF A CE space decodes, active low

dsp_a_are_n In DSP EMIF A read enable, active low

dsp_a_awe_n In DSP EMIF A write enable, active low

dsp_a_aoe_n In DSP EMIF A output enable, active low

dsp_a_ardy In DSP EMIF A ready control

dsp_a_rdout[63:0] Out DSP EMIF A read data

dsp_a_dout_en Out DSP EMIF A data output enable

dsp_a_reg Out Array of 64 32-bit registers for control and configuration

mapped into DSP EMIF A.

dsp_a_status In Array of 64 32-bit registers for status readback mapped

into DSP EMIF A.

dsp_a_rd[127:0] Out DSP EMIF A memory decodes for reads. These are

asynchronous memory locations.

dsp_a_wr[127:0] Out DSP EMIF A memory decodes for writes. These are

asynchronous memory locations.

dsp_a_ififo_dout[63:0] Out Array of outputs from DSP input FIFOs connected to the

DSP bus. The array is for one bus in the example logic.

This is for data to the logic from the DSP.

dsp_a_ififo_rd[7:0] In Array of DSP input FIFO read enables.

dsp_a_ififo_wr[7:0] Out Array of DSP input FIFO write enables.

dsp_a_ififo_rst[7:0] In Array of resets to the DSP input FIFOs.

dsp_a_ififo_rd_count[7:0] Out Array of DSP input FIFO read counts. These are how

many points each DSP input FIFO has in it. This count

is 2 clocks latent and is synchronous to d_clk.

dsp_a_ififo_wr_count[7:0] Out Array of DSP input FIFO write counts. These are how

many points each DSP input FIFO has in it. This count

is 2 clocks latent and is synchronous to dsp_aeclk.

dsp_a_ofifo_din[63:0] In Array of inputs to the DSP output FIFOs connected to

the DSP bus. The array is for one bus in the example

logic. This is for data from the logic to the DSP.

dsp_a_ofifo_rd[7:0] Out Array of DSP output FIFO read enables.

dsp_a_ofifo_wr[7:0] In Array of DSP output FIFO write enables.

Innovative Integration FrameWork Logic User Guide 81

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Cypress Semiconductor Perform CY7C1372D Guía de usuario Pagina 81