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Another built-in test method is to use data checkers in the logic sprinkled through the data chain
help to spot the source of problems. If you have a missing timing constraint or a clock domain
issue, these can be hard to catch since they may be rare. A data checker gives you a way to look
for bad data and then trigger ChipScope or the logic analyzer. In many cases, rare errors are
impossible to catch without this sort of data checker. This technique has saved time because the
trigger at the bad data point allows you to inspect all the suspect signals and find the culprit.
5.5.2 Xilinx ChipScope
Xilinx offers an excellent tool for debugging FPGA designs call ChipScope. This tool works over
the FPGA JTAG port using any of the standard Xilinx JTAG cables. Software on the PC connects
to a ChipScope logic core that you embed in your logic. This is an optional tool from Xilinx and is
not included in the standard ISE software. For its cost of under $1500, we have found it well worth
the money.
The ChipScope core allows you to monitor internal FPGA signals using triggers and a sample
clock. The number of signals you can monitor and use for triggers is set up when you generate
the ChipScope core. The core size is determined by the number of signals monitored and the
number of samples stored. If the core gets too big, it will affect your design and tends to muddle
the debug process. Sometimes it is better to have a small core that has a small footprint and
does not interfere with the other logic for this reason.
The clock is used as the sample clock for the logic so it should be synchronous to the inputs
signals or sufficiently fast to sample them accurately. The size of the core
You will interact with the ChipScope software over a JTAG cable to the target device. This link is
limited to about 4-20 Mb/s, so it is not really real-time, but rather just a means to get the data from
the FPGA to the ChipScope software. The signals are captured in the FPGA block RAMs so the
record length is somewhat short being limited in most cases to 256 to 1K points.
Because of these limitations in JTAG speed and capture size, it is important to devise triggering
methods that allow you to catch the error condition. It is common to devise a piece of error
detection logic that serves as a trigger to ChipScope to best use the capture RAM. It is possible
Innovative Integration FrameWork Logic User Guide 40
Illustration 36: Debugging with ChipScope
- FrameWork Logic Users Guide 1
- 1 Table of Contents 2
- 2 List of Figures 4
- 3 List of Tables 6
- 4 Introduction 7
- 4.4 Where to Get Help 8
- 5 Logic Development Process 9
- Hardware Interface Layer 10
- Application 11
- (your logic does here) 11
- 5.1.2 VHDL Simulation 12
- 5.2.1 Installation 20
- 5.2.2 MATLAB Simulink Use 22
- SRAM used 24
- 5.4 Loading Logic 27
- 5.4.1 JTAG 27
- 5.4.2.2 Velocia Download 38
- 5.5 Debugging 39
- 5.5.1 Built-in Test Modes 39
- 5.5.2 Xilinx ChipScope 40
- CAUTION: 41
- 6 FrameWork Designs 46
- 6.1.4.2 Memory Map 48
- R/W CE Type 49
- 6.1.4.3 Clocks 51
- 6.1.4.3.1 Clock Sources 52
- 6.1.4.3.2 Domains 53
- 6.1.4.4 A/D Interface 53
- 6.1.4.5 DAC Interface 54
- 6.1.4.6 DSP Interface 55
- 6.1.4.6.1 DSP Bus EMIF A 55
- 6.1.4.6.2 DSP Bus EMIF B 59
- 6.1.4.7 Event Log 59
- 6.1.6 Synthesis and Fitting 60
- 6.1.6.2 Constraints 61
- 6.1.6.2.1 Timing Constraints 61
- 6.1.6.3 Logic Utilization 63
- 6.1.7 Place and Route 66
- 6.1.8 Simulation 68
- 6.1.8.3 Simulation notes 70
- 6.1.9.1 Loading over PCI 70
- 6.1.9.2 Loading over JTAG 70
- 6.2 PMC UWB 71
- 6.2.1 Overview 71
- 6.2.2 Target Devices 71
- 6.2.3 Development Tools 71
- 6.2.4 Application Example 71
- 7 Framework Library 72
- 7.1.1.1 ii_quixote_adc 73
- MATLAB Simulink Component: 75
- 7.1.1.2 ii_quixote_dac 76
- Supported Platforms: Quixote 79
- Description: 79
- Port Direction Function 81
- Target Devices: any 84
- MATLAB Simulink Components: 86
- Target Devices : any 90
- Target Device : Any 94
- 8 Generic Components 95
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