Cypress Semiconductor enCoRe CY7C64215 Manual de usuario descargar pdf (Pagina 8)

August 17, 2011 Document No. 001-15340 Rev. *A

AN6073

[4:3] of the OSC_CR0 register and can range from 6 ms to

3s, depending on the value written.

Sleep and Wake-up Timer

CY7C64x13 does not have a dedicated sleep/wake-up timer.

However, the user can employ an external RC circuit con-

nected to a GPIO pin for this purpose. The selected GPIO pin

is connected to ground through a capacitor and to Vdd

through a resistor. For use, the pin is first configured to output

a low. This is achieved by writing a ‘0’ to the appropriate bit of

the port data register. The capacitor discharges through the

path created by the low output pin. The configuration register

and port data register are modified for Hi-Z and rising edge

interrupt polarity. The node is then allowed to charge up

through the resistor. When the node exceeds the threshold of

the pin, a GPIO interrupt occurs. The check for various condi-

tions can be done in the interrupt ISR. The time for the node

to rise up to the threshold depends on the time constant of

the RC network. The interrupt ISR must also contain code to

discharge the capacitor and re-enable the RC timer opera-

tion. The time constant is effectively the sleep time of the cir-

cuit. A typical RC connection for the explained setup with

capacitor charge/discharge is shown in Figure 6.

Figure 6. Typical RC Connection

In enCoRe III, the sleep timer is sourced by the 32 KHz oscil-

lator (internal low-power oscillator or external crystal). When

the internal low-power oscillator is selected as the clock

source, sleep intervals are approximate. However, the sleep

period can be configured by writing to bits [4:3] in the

OSC_CR0 register. These bits also set the watchdog period

and so the user must choose an appropriate value based on

the requirements for both sleep and watchdog period.

Timer

The CY7C64x13 has a 12-bit free-running timer that is

clocked with a 1 MHz source clock. Two interrupts are pro-

vided at 128 μs and 1.024 ms. The 1.024-ms interrupt is par-

ticularly used in timing USB events. The firmware can directly

read the 12-bit value of this register at any time. This 12-bit

The CY7C64215 (enCoRe III) has a sleep timer (sleep timer

interrupt, to wake up periodically and poll for interrupts) and

watchdog timer as part of the system resource. The sleep

timer and watchdog timer are sourced by the 32 KHz source.

Accuracy levels decrease when the ILO is chosen as the

32 KHz source. Additionally, the user can also use the digital

blocks to build 8, 16, 24 bits wide timer (depending on

resource availability). The clock for this timer can be the sys-

tem clocks, other PSoC blocks and external pins routed

through the global inputs. There is no 1-ms timer function

provided explicitly for the enCoRe III device. However, the 8-

bit PWM can be configured to function as a 1-ms timer with

interrupts. Alternatively, the VC3 clock signal can also be

configured to provide 1-ms interrupts. The enCoRe III also

provides SOF interrupts every 1 ms. The details on this are

given in the firmware porting section of this application note.

Voltage Regulator

An external 3.3V voltage regulator is required and should be

connected to the Vref pin in the CY7C64x13. An external pull

up resistor (~1.3 Kohm) should be connected between this

pin and the D+ pin. The 3.3V regulator is normally sourced by

the Vbus, due to the USB spec requirement that the pull up at

D+ should be disabled when there is a Vbus disconnect.

The CY7C64215 has an internal 3.3V regulator and an inter-

nal pull up resistor. This resistor is disabled at reset and

should be enabled by the firmware. The API function

USB_Start (Device, Operating Voltage) takes care of this in

addition to unconfiguring the device and setting it to address

0. This function also sets the proper mode for the voltage reg-

ulator (pass-through or regulating) depending on the supply

voltage—achieved by writing to the RegEnable bit (bit 0) in

USB_CR1 register (address 1,C1h). If the device is self pow-

ered, then firmware should provide Vbus detection and then

call the USB_Start function.

GPIO pin

Vdd

GPIO pin

Vdd

GPIO pin

Vdd

When pin

configured to

OUTPUT LOW

When pin

configured to Hi -Z

Capacitor

Discharge

Capacitor Charge

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

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