Cypress Semiconductor enCoRe CY7C64215 Manual de usuario descargar pdf (Pagina 4)

August 17, 2011 Document No. 001-15340 Rev. *A

AN6073

Differences Between the Two Microcontrollers

Features/Characteristics CY7C64x13 CY7C64215

CPU core M8B core M8C core

Memory Organization 8 KB PROM, 256 byte RAM 16K FLASH, 1K SRAM, 256 bytes of dedicated USB end-

point RAM

Serial Interface Engine The SIE’s response to USB packets depends on the

endpoint modes. Sends and receives data from the

appropriate endpoint FIFO, enabling/disabling flags

during this function.

The SIE’s response to USB packets depends on the end-

point modes. It sends and receives data from the USB

SRAM through the PSoC Memory Arbiter (PMA). The

PMA manages potentially conflicting SRAM access

requests from the SIE and M8C. The SIE also identifies

the Start-of-Frame (SOF) and saves the frame count. The

firmware is required to enable PMA channels before load-

ing the USB SRAM locations with IN/OUT data.

Interface I2C and HAPI interfaces possible. I2C supports a 100

KHz serial link. HAPI can support 8, 16, or 24 bits

wide bus for data transfer with an external device.

Option available to choose from hardware and software

I2C user modules. The I2C hardware is available as a

system resource and can be configured to operate using

the APIs. Neither the software nor hardware I2Cs require

digital/analog peripherals. Other communication inter-

faces that can be built using the configurable blocks are

SPI master, SPI slave and UART interface user modules.

No preconfigured user module is available for HAPI. The

developer can use the available blocks to build a HAPI

interface.

Endpoint 1 control endpoint, 4 data endpoints. The endpoints

use higher address bytes of the SRAM and the actual

value depends on the number and size of the end-

points

1 control and 4 data endpoints. Dedicated 256 byte buffer

for all the endpoints.

GPIO The GPIOs can be configured as inputs with internal

pull ups (Resistive Mode), output Low, Output High or

Hi-Z mode. Falling or rising edge interrupts can be

supported at all port pins.

Each GPIO can sink up to 25 mA of current and have con-

figurable (falling edge, rising edge and change from read)

interrupts at all GPIOs. Pull up, pull down, High-Z, Strong

or Open Drain Drive Modes on all GPIOs.

Interrupt The first lower 26 bytes of PROM are dedicated for 13

interrupt vectors.

The CPU utilizes an interrupt controller with up to 20 vec-

tors from address 0x0000 to 0x002F and then from

0x0040 to 0x0068 flash locations.

Clocking External crystal used in conjunction with the internal

PLL/oscillator or accurate external clock.

No option for external crystal. Input for external clock pro-

vided. Internal 24 MHz and 32 KHz oscillators provided.

These two oscillator frequencies together with clock divid-

ers can provide a wide range of clocks.

Reset Power on reset (POR) and watchdog reset (WDR). Power on reset (POR), watchdog reset (WDR) and Inter-

nal Reset (IRES—occurs during boot sequence when

FLASH reads are considered invalid by SROM code).

Suspend The device can be put into suspend by writing to the

Processor Status and Control Register (address

0xFF). Only the USB receiver and GPIO interrupt

logic is on. The run bit at address FF should be set to

resume the part out of suspend. The instruction fol-

lowing suspend is normally pre-fetched and so is usu-

ally programmed as a ‘nop’.

The device is put into suspend by setting the sleep bit in

the CPU_SCR0 register. The USB wake interrupt should

be enabled to enable the device to resume USB opera-

tion. Two instructions following ‘Sleep’ are pre-fetched

and so are programmed to be ‘nop’s.

Voltage regulator External voltage regulator (3.3V) required at Vref

input on the microcontroller. The pull up resistor at the

D+ pin should be provided externally to the Vref pin.

Integrated voltage regulator and pull up resistor on chip. If

the chip uses a 3.3V supply, the regulator can be put in

pass-through mode (the 3.3V reference is provided from

the supply itself).

Stack Separate Program Stack and Data Stack. Single Stack for program and data.

DAC port Has a 4-bit DAC that can be enabled to sink current

(programmable output current sink levels) or can be

used as an input with internal pull up.

The user module for DAC is not explicitly provided. How-

ever, users can build, depending on resources they can

allocate, a 4/6/8 bit programmable output sink/source cur-

rent or a DAC for programmable output voltage levels.

1 2 3 4 5 6 7 8 9 ... 15 16

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