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Cypress Semiconductor enCoRe CY7C64215 Manual de usuario Pagina 27

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CY7C64215
Document Number: 38-08036 Rev. *E Page 27 of 33
AC I
2
C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and –40°C <
T
A
< 85°C, or 3.15V to 3.5V and –40°C < T
A
< 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Figure 8. Definition for Timing for Fast-/Standard-Mode on the I
2
C Bus
Table 26. AC Characteristics of the I
2
C SDA and SCL Pins for Vdd
Parameter Description
Standard-Mode Fast-Mode
Unit Notes
Min Max Min Max
F
SCLI2C
SCL Clock Frequency 0 100 0 400 kHz
T
HDSTAI2C
Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
4.0 –0.6– μs
T
LOWI2C
LOW Period of the SCL Clock 4.7 –1.3– μs
T
HIGHI2C
HIGH Period of the SCL Clock 4.0 –0.6– μs
T
SUSTAI2C
Setup Time for a Repeated START Condition 4.7 –0.6– μs
T
HDDATI2C
Data Hold Time 0 –0– μs
T
SUDATI2C
Data Setup Time 250 – 100
[12]
–ns
T
SUSTOI2C
Setup Time for STOP Condition 4.0 –0.6– μs
T
BUFI2C
Bus Free Time Between a STOP and START
Condition
4.7 –1.3– μs
T
SPI2C
Pulse Width of spikes are suppressed by the
input filter.
– –050ns
Note
12. A Fast-Mode I
2
C-bus device can be used in a Standard-Mode I
2
C-bus system, but the requirement T
SUDATI2C
≥ 250 ns must then be met. This automatically is the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line t
rmax
+ T
SUDATI2C
= 1000 + 250 = 1250 ns (according to the Standard-Mode I
2
C-bus specification) before the SCL line is released.
SDA
SCL
S
Sr SP
T
BUFI2C
T
SPI2C
T
HDSTAI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
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