Cypress Semiconductor FX2LP Manual de usuario descargar pdf (Pagina 53)

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Document #: 38-08032 Rev. *K Page 53 of 60

10.17.4 Sequence Diagram of a Single and Burst Asynchronous Write

Figure 10-23 diagrams the timing relationship of the SLAVE

FIFO write in an asynchronous mode. The diagram shows a

single write followed by a burst write of 3 bytes and committing

the 4-byte-short packet using PKTEND.

• At t = 0 the FIFO address is applied, insuring that it meets

the set-up time of t

SFA

. If SLCS is used, it must also be

asserted (SLCS may be tied low in some applications).

• At t = 1 SLWR is asserted. SLWR must meet the minimum

active pulse of t

WRpwl

and minimum de-active pulse width

of t

WRpwh

. If the SLCS is used, it must be in asserted with

SLWR or before SLWR is asserted.

• At t = 2, data must be present on the bus t

SFD

before the

deasserting edge of SLWR.

• At t = 3, deasserting SLWR will cause the data to be written

from the data bus to the FIFO and then increments the FIFO

pointer. The FIFO flag is also updated after t

XFLG

from the

deasserting edge of SLWR.

The same sequence of events are shown for a burst write and

is indicated by the timing marks of T = 0 through 5. Note: In

the burst write mode, once SLWR is deasserted, the data is

written to the FIFO and then the FIFO pointer is incremented

to the next byte in the FIFO. The FIFO pointer is post incre-

mented.

In Figure 10-23 once the four bytes are written to the FIFO and

SLWR is deasserted, the short 4-byte packet can be

committed to the host using the PKTEND. The external device

should be designed to not assert SLWR and the PKTEND

signal at the same time. It should be designed to assert the

PKTEND after SLWR is deasserted and met the minimum

deasserted pulse width. The FIFOADDR lines are to be held

constant during the PKTEND assertion.

PKTEND

SLWR

FLAGS

DATA

Figure 10-23. Slave FIFO Asynchronous Write Sequence and Timing Diagram

[20]

WRpwh

WRpwl

XFLG

SFD

N+1

XFLG

SFA

FAH

FIFOADR

SLCS

WRpwh

WRpwl

WRpwh

WRpwl

WRpwh

WRpwl

FAH

SFA

FDH

SFD

N+2

FDH

SFD

N+3

FDH

SFD

FDH

PEpwh

PEpwl

t=0

t=2

t =1

t=3

T=0

T=2

T=1

T=3

T=6

T=9

T=5

T=8

T=4

T=7

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