Cypress Semiconductor FX2LP Manual de usuario descargar pdf (Pagina 39)

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Document #: 38-08032 Rev. *K Page 39 of 60

10.3 Data Memory Read

data in

A[15..0]

RD#

STBL

STBH

D[7..0]

data in

ACC1

[19

DSU

Stretch = 0

Stretch = 1

A[15..0]

RD#

D[7..0]

ACC1

[19]

DSU

CS#

SCSL

OE#

SOEL

Figure 10-2. Data Memory Read Timing Diagram

CLKOUT

[17]

CLKOUT

[17]

Table 10-2. Data Memory Read Parameters

Parameter Description Min. Typ. Max. Unit Notes

1/CLKOUT Frequency 20.83 ns 48 MHz

41.66 ns 24 MHz

83.2 ns 12 MHz

Delay from Clock to Valid Address 10.7 ns

STBL

Clock to RD LOW 11 ns

STBH

Clock to RD HIGH 11 ns

SCSL

Clock to CS LOW 13 ns

SOEL

Clock to OE LOW 11.1 ns

DSU

Data Set-up to Clock 9.6 ns

Data Hold Time 0 ns

When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 will only be active while

either RD# or WR# are active. The address of AUTOPTR2 will be active throughout the cycle and meet the above address valid

time for which is based on the stretch value

Note:

19. t

ACC2

and t

ACC3

are computed from the above parameters as follows:

ACC2

(24 MHz) = 3*t

– t

–t

DSU

= 106 ns

ACC2

(48 MHz) = 3*t

– t

DSU

= 43 ns

ACC3

(24 MHz) = 5*t

– t

–t

DSU

= 190 ns

ACC3

(48 MHz) = 5*t

– t

DSU

= 86 ns.

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Cypress Semiconductor FX2LP Manual de usuario Pagina 39

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