Cypress Semiconductor CY8C21534 Especificaciones descargar pdf (Pagina 18)

Figure 8 shows the layout of these analogue and digital blocks and the basic

structuring that the designer has to work with.

Figure 8: PSoC Designer Digital and Analogue Blocks. Screenshot [3].

As figure 8 shows these blocks, once placed, can then be interconnected with visual

routing. All busses that are available for use are visible as well as external pins that

might need to be accessed by the user. If several inputs were to be multiplexed into a

single block, this could be achieved through the visual routing and configuration of

the PSoC Designer software. However, bus comparators are also available for logical

operations of inputs or outputs.

Each block will also give available options for the clock inputs. These can be set to the

system clock, a divider of the system clock, a pulse width modulator, or an external

clock input. With each block there also comes a set of parameters that can be

configured. For example, an SPI Master block will allow the user to set which pins are

used for SS, MISO, MOSI, and SCK. Additionally, it gives the options of which clock to

synchronize to and whether the output should be inverted.

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Cypress Semiconductor CY8C21534 Especificaciones Pagina 18