Cypress Semiconductor STK11C68-5 Manual de usuario descargar pdf (Pagina 11)

STK11C68

Document Number: 001-50638 Rev. *C Page 11 of 15

Software Controlled STORE/RECALL Cycle

The software controlled STORE/RECALL cycle follows.

[10, 11]

Parameter Alt Description

25 ns 35 ns 45 ns

Unit

Min Max Min Max Min Max

AVAV

STORE/RECALL Initiation Cycle Time 25 35 45 ns

[10]

AVEL

Address Setup Time 0 0 0 ns

[10]

ELEH

Clock Pulse Width 20 25 30 ns

HACE

[10]

ELAX

Address Hold Time 20 20 20 ns

RECALL

[10]

RECALL Duration 20 20 20 μs

Switching Waveform

Figure 10. CE Controlled Software STORE/RECALL Cycle

[11]

SCE

HACE

STORE

/ t

RECALL

DATA VALID

6#SSERDDA1#SSERDDA

HIGH IMPEDANCE

ADDRESS

DQ (DATA)

Notes

10. The software sequence is clocked on the falling edge of CE

without involving OE (double clocking aborts the sequence).

11. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE

must be HIGH during all six consecutive cycles.

Not recommended for new designs.

In production to support ongoing production programs.

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