Cypress Semiconductor Perform nvSRAM Especificaciones descargar pdf (Pagina 20)

CY14B256KA

Document Number: 001-55720 Rev. *H Page 20 of 28

Figure 9. SRAM Read Cycle #2 (CE and OE Controlled)

[25, 26]

Figure 10. SRAM Write Cycle #1 (WE Controlled)

[26, 27, 28]

Figure 11. SRAM Write Cycle #2 (CE Controlled)

[26, 27, 28]

Switching Waveforms (continued)

Address ValidAddress

Data Output

Output Data Valid

Standby

Active

High Impedance

HZCE

ACE

LZCE

DOE

LZOE

HZOE

Data Output

Data Input

Input Data Valid

High Impedance

Address ValidAddress

Previous Data

SCE

PWE

HZWE

LZWE

Data Output

Data Input

Input Data Valid

High Impedance

Address Valid

Address

SCE

PWE

Notes

25. WE

must be HIGH during SRAM read cycles.

26. HSB

must remain HIGH during Read and Write cycles.

27. If WE

is low when CE goes low, the outputs remain in the high impedance state.

28. CE

or WE must be >V

during address transitions.

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Real Time Clock 1
Calibrating the Clock 8
Watchdog Timer 8
CY14B256KA 10
[25, 26] 20
[26, 27, 28] 20
[41, 42] 23
Units of Measure 26

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Cypress Semiconductor Perform nvSRAM Especificaciones Pagina 20

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