Cypress Semiconductor Perform CY7C68013 Especificaciones descargar pdf (Pagina 2)

Migrating From EZ-USB FX2™ to EZ-USB FX2LP™

The FX2LP can use the same filter network as the FX2 for

AVCC. The FX2LP analog ground (pin 20 in 128-pin package)

does not need to be isolated. It can be connected to the digital

ground. Other changes made to the chip do not affect all

designs.

Feature Changes

An overview of the feature changes/additions in the FX2LP

(CY7C68013A) are listed below:

• Lower power

• Enabling pull-up on D+

• Disabling high speed chirp via EEPROM config byte

• Expanded internal code/data RAM

• ECC generation on GPIF data

• Zero-length in-packets with no firmware intervention and

Data PID sequencing in isochronous IN transfers

• Additional Package with more GPIOs (CY7C68015A).

Lower Power

The FX2LP uses a different process then the FX2. The major

result of this change is to reduce the power consumption of

the chip. The lower current is obtained just by using the

FX2LP with the required crystal modifications. This configu-

ration meets all USB bus powered requirements of uncon-

figured current (100 mA) and suspend current (500 µA).

As a result of this lower power, to meet the unconfigured

current limit, it is no longer necessary to use the double

enumeration procedure where the device first enumerates in

full speed with a current draw below 100 mA and then discon-

nects and reconnects as a high speed device as described in

the application note Bus-Powered Enumeration with the FX2.

If an existing design uses this procedure the designer MUST

remove the procedure in design. For new designs using

FX2LP, there is no concern as the part does meet the 100-mA

limitation requirement for unconfigured current while

operating in either full or high speed.

Enabling Pull-up on D+

There is a minor difference with respect to when the internal

logic enables the pull up on D+ to signal an attach event to

the host. In the case of the FX2, the pull-up on D+ is enabled

on power-up. In the case of the FX2LP, the pull-up on D+ is

enabled when the reset is released (in a deasserted state).

On plug in, the FX2 enables the pull-up on D+ signaling at

attach event to the host. If the reset is held active for longer

than 100 ms, an attach signal will be sent to the host and the

host will begin its enumeration sequence (after 100 ms from

when the attach is detected), while the FX2 is still held in

reset. Section 7.1.7.3 (page 150) of the USB 2.0 specification,

provides further information on the debounce interval (delta

t3). While using the FX2 Cypress recommends that a reset

time of 10 ms with an RC network of 100K/0.1 µF be used.

The FX2LP has a more flexible reset timing requirement. As

the FX2LP enables the pull-up n the D+ once the RESET is

deasserted, there really is no restriction on the reset timing as

the host will only receive an attach signal when the RESET is

released.l

Disabling High Speed Chirp via EEPROM Config Byte

During power-on sequence, the operating speed of the FX2

device defaults to high-speed. The FX2 device has the

capability of disabling the high-speed chirp state machine

using the Cypress internal register CT1. The 8051 can set or

clear bit 1 of the CT1 register anytime. On re-enumeration

(disconnecting and then reconnecting) the FX2 device will

enumerate with the chirp state machine disabled if this bit of

the CT1 register is set to 1. So on a disconnect event followed

by a re-connect, the device will re-enumerate as a full-speed

only device.

The chirp state machine can also be disabled on power-up,

by setting bit 7 of the configuration byte of the EEPROM.

During power-up sequence, the core will copy this bit setting

to bit 1of the CT1 register and the device will enumerate as a

full-speed device. Once enumerated as a full-speed device,

the 8051 may enable the chirp state machine anytime by

clearing bit 1 of the CT1 register. On re-enumeration the

same device will enumerate as a high-speed device.

In the case of FX2LP, the device also defaults to the

high-speed mode of operation: bit 1 of the CT1 register

defaults to 0. After the device has powered-up with the chirp

state machine enabled (default), it can be switched to a

different mode of operation by having the 8051 change bit 1

of the CT1 register.

If no EEPROM is used, the device will operate in its default

high-speed mode. If using an EEPROM, the chirp state

machine status is determined by the setting of bit 7 of the

configuration byte of the EEPROM. The behavior of the

FX2LP chirp state machine is different than the FX2 when bit

7 of the configuration byte of the EEPROM is set to 1 (chirp

state disabled on power-up).

The CT1 register and the EEPROM control bit (bit 7 of the

configuration byte) behave differently in FX2LP than in FX2.

In FX2, if the EEPROM control bit that forces USB full-speed

operation is set, FX2 comes up in full-speed mode, and upon

re-enumeration FX2 is capable of re-enumerating on the USB

bus in high-speed mode (if the 8051 has cleared bit 1 of the

CT1 register to enable high-speed mode). In the case of

FX2LP, if the full-speed control bit of the EEPROM is set, the

device will ONLY come up in full speed mode, even after USB

re-enumeration.Setting or clearing this bit by the 8051 has no

effect on enabling or disabling the chirp state machine when

bit 7 of the configuration byte of the EEPROM is set to 1. If it

is set to 0, FX2LP behaves the same as the FX2. In other

words when bit 7 of configuration byte is set to 0 (chirp

enabled) the FX2LP comes up in high speed mode and the

8051 may switch the mode by changing bit 1 of CT1 register

anytime followed by a disconnect and reconnect event.

If the existing FX2 application is bus powered and uses the

double enumeration sequence (which is a recommended

workaround) to meet the unconfigured current requirements

of the USB-IF compliance test, then the application will not

behave the same when replaced with the FX2LP. If replacing

the part with FX2LP, when the device enumerates with the

high speed chirp disabled (control bit of the configuration byte

of the EEPROM set), on renumeration, the device will fail to

enumerate as a high speed device even though the 8051 had

cleared bit 1 of the CT1 register. As stated in the “Bus

Powered Enumeration with FX2” application note, the full

speed mode trick upon initial plug was done to get the uncon-

figured power down to the 100-mA range. As FX2LP power

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