
Document #: 38-05445 Rev. *H Page 3 of 17
Pin Configuration
Figure 1. 48-Ball VFBGA (Top View)
[2]
Figure 2. 44-Pin TSOP II (Top View)
[3]
Figure 3. 48-Pin TSOP I (512K x 16/1M x 8) (Top View)
[2, 4]
WE
V
CC
A
11
A
10
NC
A
6
A
0
A
3
CE
1
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
V
SS
A
7
I/O
0
BHE
CE
2
A
2
A
1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
A
18
NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A
16
A
17
1
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
18
17
20
19
27
28
25
26
22
21
23
24
10
A
5
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
17
A
18
A
9
A
10
A
11
A
12
A
15
A
16
A
14
A
13
OE
BHE
BLE
CE
WE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
V
CC
V
SS
V
SS
A
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE
Vss
I/O15/A19
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Product Portfolio
Product Range
V
CC
Range (V)
Speed
(ns)
Power Dissipation
Operating I
CC
, (mA)
Standby, I
SB2
(A)
f = 1 MHz f = f
max
Min Typ
[1]
Max Typ
[1]
Max Typ
[1]
Max Typ
[1]
Max
CY62157EV30LL Industrial/
Auto-A
2.2 3.0 3.6 45 1.8 3 18 25 2 8
Auto-E 2.2 3.0 3.6 55 1.8 4 18 35 2 30
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25°C.
2. NC pins are not connected on the die.
3. The 44-TSOP II package has only one chip enable (CE
) pin.
4. The BYTE
pin in the 48-TSOP I package must be tied HIGH to use the device as a 512K × 16 SRAM. The 48-TSOP I package can also be used as a 1M × 8
SRAM by tying the BYTE
signal LOW. In the 1M x 8 configuration, Pin 45 is A19, while BHE, BLE and I/O8 to I/O14 pins are not used (NC).
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