Cypress Semiconductor CY7C1354CV25 Manual de usuario descargar pdf (Pagina 22)

CY7C1354CV25

CY7C1356CV25

Document Number: 38-05537 Rev. *M Page 22 of 33

Switching Characteristics

Over the Operating Range

Parameter

[20, 21]

Description

-250 -200 -166

Unit

Min Max Min Max Min Max

Power

[22]

(typical) to the first access read or

write

1–1–1–ms

Clock

CYC

Clock cycle time 4.0–5–6–ns

MAX

Maximum operating frequency – 250 – 200 – 166 MHz

Clock HIGH 1.8 – 2.0 – 2.4 – ns

Clock LOW 1.8 – 2.0 – 2.4 – ns

Output Times

Data output valid after CLK rise – 2.8 – 3.2 – 3.5 ns

EOV

OE LOW to output valid – 2.8 – 3.2 – 3.5 ns

DOH

Data output hold after CLK rise 1.25 – 1.5 – 1.5 – ns

CHZ

Clock to high Z

[23, 24, 25]

1.25 2.8 1.5 3.2 1.5 3.5 ns

CLZ

Clock to low Z

[23, 24, 25]

1.25 – 1.5 – 1.5 – ns

EOHZ

HIGH to output high Z

[23, 24, 25]

– 2.8 – 3.2 – 3.5 ns

EOLZ

OE LOW to output low Z

[23, 24, 25]

0–0–0–ns

Set-up Times

Address set-up before CLK rise 1.4 – 1.5 – 1.5 – ns

Data input set-up before CLK rise 1.4 – 1.5 – 1.5 – ns

CENS

CEN set-up before CLK rise 1.4 – 1.5 – 1.5 – ns

WES

WE, BW

set-up before CLK rise 1.4 – 1.5 – 1.5 – ns

ALS

ADV/LD set-up before CLK rise 1.4 – 1.5 – 1.5 – ns

CES

Chip select set-up 1.4 – 1.5 – 1.5 – ns

Hold Times

Address hold after CLK rise 0.4 – 0.5 – 0.5 – ns

Data input hold after CLK rise 0.4 – 0.5 – 0.5 – ns

CENH

CEN hold after CLK rise 0.4 – 0.5 – 0.5 – ns

WEH

WE, BW

hold after CLK rise 0.4–0.5–0.5–ns

ALH

ADV/LD hold after CLK rise 0.4 – 0.5 – 0.5 – ns

CEH

Chip select hold after CLK rise 0.4 – 0.5 – 0.5 – ns

Notes

20. Timing reference level is when V

DDQ

= 2.5 V.

21. Test conditions shown in (a) of Figure 4 on page 21 unless otherwise noted.

22. This part has a voltage regulator internally; t

power

is the time power needs to be supplied above V

minimum initially, before a Read or Write operation can be initiated.

23. t

CHZ

, t

CLZ

, t

EOLZ

, and t

EOHZ

are specified with AC test conditions shown in (b) of Figure 4 on page 21. Transition is measured ± 200 mV from steady-state voltage.

24. At any given voltage and temperature, t

EOHZ

is less than t

EOLZ

and t

CHZ

is less than t

CLZ

to eliminate bus contention between SRAMs when sharing the same data

bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve

high Z prior to low Z under the same system conditions.

25. This parameter is sampled and not 100% tested.

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 32 33

CY7C1354CV25 1
CY7C1356CV25 1

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