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Interfacing SRAM with FX2LP over GPIF

November 4, 2009 Document No. 001-57322 Rev. ** 1

AN57322

Author: Bhuvaneswara Rao Nalla, Praveen Kumar C P

Associated Project: Yes

Associated Part Family: CY7C68013A

Software Version: None

Associated Application Notes: None

Application Note Abstract

This application note discusses how to connect Cypress SRAM CY7C1399B to FX2LP over the General Programmable

Interface (GPIF). It describes how to create read and write waveforms using the GPIF Designer. This application note is also

useful as a reference to connect FX2LP to other SRAMs.

Introduction

The GPIF is an 8-bit or 16-bit programmable parallel

interface that helps to reduce system costs by providing a

glueless interface between the EZ-USB FX2LP™ and an

external peripheral. It is a highly configurable and flexible

piece of hardware that allows you to get the most out of

your USB 2.0 design. GPIF fits into applications that need

an external mastering device to exchange information.

The GPIF allows the EZ-USB FX2LP to perform local bus

mastering to external peripherals implementing a wide

variety of protocols. For example, EIDE/ATAPI, printer

parallel port (IEEE P1284), Utopia, and other interfaces

are supported using the GPIF block of the EZ-USB

FX2LP.

GPIF Designer is a utility that Cypress provides to create

GPIF waveform descriptors. This is done according to the

read and write cycle timing of the peripherals, to connect

them with FX2LP. When created, these waveforms can be

exported to a C file, which is included into the project

workspace. This document explains the process of

defining the interface, creating waveforms, exporting them,

and including them in the project framework. Familiarity

with the examples and documentation on the EZ-USB

FX2LP development kit and Chapter10 (GPIF) of the EZ-

USB FX2LP Technical Reference Manual is beneficial in

designing the waveforms.

Hardware Connections

This section discusses the required hardware interconnect

between FX2LP and the SRAM. According to the SRAM

data sheet, communicating with this device requires three

control signals, an address, and a data bus. The SRAM‟s

three control signals are a chip enable, CE/, an output

enable OE/, and a write enable WE/. The address and

data buses are fifteen and eight bits wide, respectively. To

address memory locations greater than 512 (only 9 bit

address bus is provided by GPIF Designer) additional port

I/O pins are required. Therefore, PA[7:4] is wired to

A[12:9] and PA[1:0] is wired to A[14:13].

PA[7:4] is used to control A[12:9]. This gives the firmware

access to 16, 512 byte banks for a total contiguous space

of 8K. PA0 and PA1 are used to access four such 8K byte

banks, providing access to the entire 32K of space.

Note Only A[8:0] is shown in this document because the

GPIF only has nine address lines.

Figure 1. Hardware Connection Diagram

[+] Feedback

1 2 3 4 5 6 ... 15 16

Indice de contenidos

Pagina 1 - AN57322

Interfacing SRAM with FX2LP over GPIF November 4, 2009 Document No. 001-57322 Rev. ** 1 AN57322 Author: Bhuvaneswara Rao Nalla, Praveen Kumar C

Pagina 2 -  Subst TC for RDY5

AN57322 November 4, 2009 Document No. 001-57322 Rev. ** 10 Testing with CyConsole The functionality of the project created is verified using the C

Pagina 3 - GPIF Waveforms

AN57322 November 4, 2009 Document No. 001-57322 Rev. ** 11 Appendix A #define VX_BB 0xBB // GPIF write #define VX_BC 0xBC // GPIF read #define G

Pagina 4

AN57322 November 4, 2009 Document No. 001-57322 Rev. ** 12 FIFORESET = 0x00; // clear NAKALL bit to resume normal operation SYNCDELAY; EP2

Pagina 5 - Read Waveform

AN57322 November 4, 2009 Document No. 001-57322 Rev. ** 13 if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE

Pagina 6

AN57322 November 4, 2009 Document No. 001-57322 Rev. ** 14 GPIFADRH = SETUPDAT[3]; // set GPIFADR[8:0] to address passe

Pagina 7 - Exporting GPIF Waveforms

AN57322 November 4, 2009 Document No. 001-57322 Rev. ** 15 IOA = ( ( ( IOA >> 4 ) + 1 ) << 4 ); // increment the ban

Pagina 8 -  INC Folder:

AN57322 November 4, 2009 Document No. 001-57322 Rev. ** 16 About the Author Name: Praveen Kumar C P Title: Applications Engineer Contact: cppk@Cyp

Pagina 9

AN57322 November 4, 2009 Document No. 001-57322 Rev. ** 2 Designing GPIF Interconnect The GPIF Designer utility is used to create the waveform des

Pagina 10 - Testing with CyConsole

AN57322 November 4, 2009 Document No. 001-57322 Rev. ** 3 The window appears as follows. Click OK. 9. Right-click on the ‟48 MHz CLK‟. Unc

Pagina 11 - Appendix A

AN57322 November 4, 2009 Document No. 001-57322 Rev. ** 4 Parameter Time (ns) Notes tWC (Write Cycle Time) (min) 12 When IFCLK=48 MHz, each GPIF c

Pagina 12 - [+] Feedback

AN57322 November 4, 2009 Document No. 001-57322 Rev. ** 5 8. A DP must be implemented after s0. To do this, set an action point on the Status

Pagina 13

AN57322 November 4, 2009 Document No. 001-57322 Rev. ** 6 Parameter Time (ns) Notes tRC - Read Cycle Time (min) 12 When IFCLK=48 MHz, each GPIF cy

Pagina 14

AN57322 November 4, 2009 Document No. 001-57322 Rev. ** 7 9. Next, add a decision point (DP) state to loop through this waveform until the GP

Pagina 15 - Summary

AN57322 November 4, 2009 Document No. 001-57322 Rev. ** 8 6. Go to Project > New Project. The tool prompts you to name the project and save i

Pagina 16 - Document History

AN57322 November 4, 2009 Document No. 001-57322 Rev. ** 9 12. Go to Project > Options for Target ‘Target1’. Select the Output tab and check th

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