Cypress Semiconductor FX2LP Especificaciones descargar pdf (Pagina 4)

Migrating From EZ-USB FX2™ to EZ-USB FX2LP™

www.cypress.com Document No. 001-42079 Rev. *D 4

operation the load capacitance of the crystal should be 12

pF.

Minimum Reset Time

The minimum reset time speed for the FX2LP part is 5 ms.

The FX2 was designed with a minimum reset time of 1.91

ms.

Ramp-up Time

To obtain the power savings, the FX2LP parts use a core

that is powered from 1.8 V. To maintain common power

sources with the FX2LP silicon, this voltage is derived

from the 3.3 V input. To properly power the internal

regulator the 3.3 V input must have a limit on the power

ramp-up rate. This means the input must turn on to a valid

voltage (3.0 V to 3.6 V) over a 200-s period. This equates

to an 18 V per/ms ramp rate. Powering up the input too

quickly latches the internal regulator and cause issues in

powering up the core. Many 3.3 V regulators have turn-on

times that are long enough to properly power-up the

internal regulator. One such regulator from Linear

Technology is the LT1763CS8-3.3.

Changes on AVCC/AGND Pin Functionality

There are no major changes as far the PCB is concerned.

Both FX2 and FX2LP run on a single 3.3 V supply. There

are two additional AVCC/AGND pins on the FX2LP that

can be rerouted on the PCB to provide additional filtering.

These two additional pins exist in the 56-, 100-, and 128-

pin packages.

For the 128-pin TQFP package, AVCC is pin 17 (was VCC

on the FX2), and AGND is pin 20 (was GND on the FX2).

Pin 17 of the FX2LP128 pin package does not need a

duplicate of the pin 10 AVCC filter network. It can be wired

in parallel to pin 10.

The FX2LP can use the same filter network as the FX2 for

AVCC. The FX2LP analog ground (pin 20 in 128 pin

package) does not need to be isolated. It can be

connected to the digital ground. Other changes made to

the chip do not affect all designs.

Details of Firmware Changes

This section highlights major improvements and changes

in FX2LP that may affect the older FX2 design while

migrating to FX2LP. Most of these do not affect your

design. The information given here is the evaluation on

how it may affect your application design. An overview of

these features is listed as follows:



Disabling high-speed chirp via EEPROM config byte



Automatic Disconnect and reconnect on a hard reset



Expanded internal code/data RAM



Zero-length packets with no firmware intervention and

Data PID sequencing in isochronous IN transfers

Disabling High-speed Chirp via EEPROM

Config Byte

During power-on sequence, the operating speed of the

FX2 device defaults to high-speed. The FX2 device has

the capability of disabling the high-speed chirp state

machine using the Cypress internal register CT1. The

8051 can set or clear bit 1 of the CT1 register anytime. On

re-enumeration (disconnecting and then reconnecting) the

FX2 device enumerates with the chirp state machine

disabled if this bit of the CT1 register is set to 1. Therefore,

on a disconnect event followed by a re-connect, the device

re-enumerates as a full-speed only device.

The chirp state machine can also be disabled on power-

up, by setting bit 7 of the configuration byte of the

EEPROM. During power-up sequence, the core copies

this bit setting to bit 1 of the CT1 register and the device

enumerates as a full-speed device. After enumerating as a

full-speed device, the 8051 may enable the chirp state

machine anytime by clearing bit 1 of the CT1 register. On

re-enumeration the same device enumerates as a high-

speed device.

In the case of FX2LP, the device also defaults to a high-

speed mode of operation: bit 1 of the CT1 register defaults

to 0. After the device has powered-up with the chirp state

machine enabled (default), it can be switched to a different

mode of operation by having the 8051 change bit 1 of the

CT1 register.

If no EEPROM is used, the device operates in its default

high-speed mode. If using an EEPROM, the chirp state

machine status is determined by the setting of bit 7 of the

configuration byte of the EEPROM. The behavior of the

FX2LP chirp state machine is different than the FX2 when

bit 7 of the configuration byte of the EEPROM is set to 1

(chirp state disabled on power-up).

The CT1 register and the EEPROM control bit (bit 7 of the

configuration byte) behave differently in FX2LP than in

FX2. In FX2, if the EEPROM control bit that forces USB

full-speed operation is set, FX2 comes up in full-speed

mode, and upon re-enumeration FX2 is capable of re-

enumerating on the USB bus in high-speed mode (if the

8051 has cleared bit 1 of the CT1 register to enable high-

speed mode). In the case of FX2LP, if the full-speed

control bit of the EEPROM is set, the device ONLY comes

up in full speed mode, even after USB re-enumeration.

Setting or clearing this bit by the 8051 has no effect on

enabling or disabling the chirp state machine when bit 7 of

the configuration byte of the EEPROM is set to 1. If it is

set to 0, FX2LP behaves the same as the FX2. In other

words when bit 7 of configuration byte is set to 0 (chirp

enabled) the FX2LP comes up in high-speed mode and

the 8051 may switch the mode by changing bit 1 of CT1

event.

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