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EZ-USB Development Kit Manual - Getting Started

Page -10 EZ-USB Development Kit Manual - Getting Started Rev 1.0

• High speed EZ-USB strobe signals (PSEN, WR#, CLKOUT, IFCLK, and RD#) are con-

nected to pin 3 of each of the five connectors P1-P6, so that they may be used as the logic

analyzer clock CLK1.

• CLK2 is not used. Instead, each connector brings 3.3V power from the EZ-USB Develop-

ment Board up to the prototype board using pin 2.

• The signals are logically grouped. For example, the 8051 address bus is on P5, and the

EZ-USB FIFO data (which shares PORTB and PORTD pins) is on P1.

Because the 20-pin headers on the proto-typing board are stackable, it is possible to build custom

circuitry on the proto board, plug the board into the EZ-USB Development board, and still plug

logic analyzer pods into the six connectors P1-P6.

Tables 4-9 show the EZ-USB pin designations for P1 through P6. For dual-mode pins, the power-

on default signal names are shown in bold type, and the alternate pin names are shown in the out-

side columns.

Table 4.

Alternate Default P1 Default Alternate

N.C. 1 2 3.3V

PSEN# 3 4 PD7 FD[15]

FD[14] PD65 6PD5 FD[13]

FD[12] PD47 8PD3 FD[11]

FD[10] PD2 9 10 PD1 FD[9]

FD[8] PD0 11 12 PB7 FD[7]

FD[6] PB61314PB5 FD[5]

FD[4] PB41516PB3 FD[3]

FD[2] PB21718PB1 FD[1]

FD[0] PB01920GND

Table 5.

Alternate

Default P2 Default Alternate

N.C. 1 2 3.3V

N.C. 3 4 RDY1 SLWR

SLRD RDY05 6CTL5

CTL4 7 8 CTL3

FLAGC CTL2 9 10 CTL1 FLAGB

FLAGA CTL0 11 12 PA7 FLAGD

PKTEND PA61314PA5 FIFOADR1

FIFOADR0 PA41516PA3 WU2

SLOE PA21718PA1 INT1#

INT0# PA01920GND

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 27 28

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Cypress Semiconductor FX2LP Guía de instalación Pagina 14