Cypress Semiconductor CY7C1480V25 Manual de usuario descargar pdf (Pagina 31)

Chapter 2: Board Components 2–23

Configuration, Status, and Setup Elements

September 2010 Altera Corporation 100G Development Kit, Stratix IV GT Edition Reference Manual

Table 2–13 lists the board settings DIP switch component reference and

manufacturing information.

SW2.5

Selects SMA or PLL for the

differential clock that goes to the

global clock inputs of clock B tree

structure.

DIFFCLKB_SEL

2.5-V

U18.3

1: PLL input

0: SMA input

SW2.6

Selects SMA or PLL that goes to the

transceivers of clock B tree structure.

REFCLKB_SEL

U20.28

1: SMA input

0: PLL input

SW2.7

Selects SMA or PLL for the

single-ended clock that goes to the

global clock inputs of clock B tree

structure.

SE_CLKB_SEL

U17.3

1: SMA input

0: PLL input

SW2.8

Enables the 644.53125-MHz clock. CLK644_EN

X1.1

1: Enabled

0: Disabled

Note to Table 2–12:

(1) When the switch is in the OFF position, a logic 1 is selected while in the ON position, a logic 0 is selected.

Table 2–12. Board Settings DIP Switch Controls

Board

Reference

Description

Schematic Signal

Name

I/O

Standard

Other

Connections

Settings (1)

Table 2–13. Board Settings DIP Switch Component References and Manufacturing Information

Board

Reference

Device Description Manufacturer

Manufacturer

Part Number

Manufacturer Website

SW2 DIP switch Grayhill Corporation 76SB08ST www.grayhill.com

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 79 80

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Cypress Semiconductor CY7C1480V25 Manual de usuario Pagina 31

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