Cypress Semiconductor CY2291 Manual de usuario descargar pdf (Pagina 10)

CY2291

Document #: 38-07189 Rev. *A Page 10 of 14

Switching Characteristics, Industrial 3.3V

Parameter Name Description Min. Typ. Max. Unit

Output Period Clock output range, 3.3V

operation

CY2291I 15

(66.6 MHz)

13000

(76.923 kHz)

CY2291FI 16.66

(60 MHz)

13000

(76.923 kHz)

Output Duty

Cycle

[11]

Duty cycle for outputs, defined as t

÷ t

[12]

OUT

> 66 MHZ

40% 50% 60%

Duty cycle for outputs, defined as t

÷ t

[12]

OUT

< 66 MHZ

45% 50% 55%

Rise Time Output clock rise time

[13]

35ns

Fall Time Output clock fall time

[13]

2.5 4 ns

Output Disable

Time

Time for output to enter three-state mode after

SHUTDOWN/OE goes LOW

10 15 ns

Output Enable

Time

Time for output to leave three-state mode after

SHUTDOWN

/OE goes HIGH

10 15 ns

Skew Skew delay between any identical or related out-

puts

[3, 12, 15]

< 0.25 0.5 ns

CPUCLK Slew Frequency transition rate 1.0 20.0 MHz/

Clock Jitter

[14]

Peak-to-peak period jitter (t

Max. – t

min.),%

of clock period (f

OUT

< 4 MHz)

<0.5 1 %

Clock Jitter

[14]

Peak-to-peak period jitter (t

Max. – t

min.)

(4 MHz <

OUT

< 16 MHz)

<0.7 1 ns

Clock Jitter

[14]

Peak-to-peak period jitter

(16 MHz < f

OUT

50 MHz)

<400 500 ps

Clock Jitter

[14]

Peak-to-peak period jitter

OUT

> 50 MHz)

<250 350 ps

10A

Lock Time for

CPLL

Lock Time from Power-Up <25 50 ms

10B

Lock Time for

UPLL and SPLL

Lock Time from Power-Up <0.25 1 ms

Slew Limits CPU PLL Slew Limits CY2291I 8 66.6 MHz

CY2291FI 8 60 MHz

Switching Waveforms

All Outputs, Duty Cycle and Rise/Fall Time

OUTPUT

[+] Feedback

1 2 ... 5 6 7 8 9 10 11 12 13 14

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